1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36/* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77/* 78 * The 3c90x series chips use a bus-master DMA interface for transferring 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101#ifdef HAVE_KERNEL_OPTION_HEADERS 102#include "opt_device_polling.h" 103#endif 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/sockio.h> 108#include <sys/endian.h> 109#include <sys/kernel.h> 110#include <sys/malloc.h> 111#include <sys/mbuf.h> 112#include <sys/module.h> 113#include <sys/socket.h> 114#include <sys/taskqueue.h> 115 116#include <net/if.h> 117#include <net/if_var.h> 118#include <net/if_arp.h> 119#include <net/ethernet.h> 120#include <net/if_dl.h> 121#include <net/if_media.h> 122#include <net/if_types.h> 123 124#include <net/bpf.h> 125 126#include <machine/bus.h> 127#include <machine/resource.h> 128#include <sys/bus.h> 129#include <sys/rman.h> 130 131#include <dev/mii/mii.h> 132#include <dev/mii/mii_bitbang.h> 133#include <dev/mii/miivar.h> 134 135#include <dev/pci/pcireg.h> 136#include <dev/pci/pcivar.h> 137 138MODULE_DEPEND(xl, pci, 1, 1, 1); 139MODULE_DEPEND(xl, ether, 1, 1, 1); 140MODULE_DEPEND(xl, miibus, 1, 1, 1); 141 142/* "device miibus" required. See GENERIC if you get errors here. */ 143#include "miibus_if.h" 144 145#include <dev/xl/if_xlreg.h> 146 147/* 148 * TX Checksumming is disabled by default for two reasons: 149 * - TX Checksumming will occasionally produce corrupt packets 150 * - TX Checksumming seems to reduce performance 151 * 152 * Only 905B/C cards were reported to have this problem, it is possible 153 * that later chips _may_ be immune. 154 */ 155#define XL905B_TXCSUM_BROKEN 1 156 157#ifdef XL905B_TXCSUM_BROKEN 158#define XL905B_CSUM_FEATURES 0 159#else 160#define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161#endif 162 163/* 164 * Various supported device vendors/types and their names. 165 */ 166static const struct xl_type xl_devs[] = { 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 168 "3Com 3c900-TPO Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 170 "3Com 3c900-COMBO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 172 "3Com 3c905-TX Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 174 "3Com 3c905-T4 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 176 "3Com 3c900B-TPO Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 178 "3Com 3c900B-COMBO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 180 "3Com 3c900B-TPC Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 182 "3Com 3c900B-FL Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 184 "3Com 3c905B-TX Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 186 "3Com 3c905B-T4 Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 188 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 190 "3Com 3c905B-COMBO Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 192 "3Com 3c905C-TX Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 198 "3Com 3c980 Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 200 "3Com 3c980C Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 202 "3Com 3cSOHO100-TX OfficeConnect" }, 203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 204 "3Com 3c450-TX HomeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 206 "3Com 3c555 Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 208 "3Com 3c556 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 210 "3Com 3c556B Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 212 "3Com 3c575TX Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 214 "3Com 3c575B Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 216 "3Com 3c575C Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 218 "3Com 3c656 Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 220 "3Com 3c656B Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 222 "3Com 3c656C Fast Etherlink XL" }, 223 { 0, 0, NULL } 224}; 225 226static int xl_probe(device_t); 227static int xl_attach(device_t); 228static int xl_detach(device_t); 229 230static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 231static void xl_tick(void *); 232static void xl_stats_update(struct xl_softc *); 233static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 234static int xl_rxeof(struct xl_softc *); 235static void xl_rxeof_task(void *, int); 236static int xl_rx_resync(struct xl_softc *); 237static void xl_txeof(struct xl_softc *); 238static void xl_txeof_90xB(struct xl_softc *); 239static void xl_txeoc(struct xl_softc *); 240static void xl_intr(void *); 241static void xl_start(if_t); 242static void xl_start_locked(if_t); 243static void xl_start_90xB_locked(if_t); 244static int xl_ioctl(if_t, u_long, caddr_t); 245static void xl_init(void *); 246static void xl_init_locked(struct xl_softc *); 247static void xl_stop(struct xl_softc *); 248static int xl_watchdog(struct xl_softc *); 249static int xl_shutdown(device_t); 250static int xl_suspend(device_t); 251static int xl_resume(device_t); 252static void xl_setwol(struct xl_softc *); 253 254#ifdef DEVICE_POLLING 255static int xl_poll(if_t ifp, enum poll_cmd cmd, int count); 256static int xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count); 257#endif 258 259static int xl_ifmedia_upd(if_t); 260static void xl_ifmedia_sts(if_t, struct ifmediareq *); 261 262static int xl_eeprom_wait(struct xl_softc *); 263static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 264 265static void xl_rxfilter(struct xl_softc *); 266static void xl_rxfilter_90x(struct xl_softc *); 267static void xl_rxfilter_90xB(struct xl_softc *); 268static void xl_setcfg(struct xl_softc *); 269static void xl_setmode(struct xl_softc *, int); 270static void xl_reset(struct xl_softc *); 271static int xl_list_rx_init(struct xl_softc *); 272static int xl_list_tx_init(struct xl_softc *); 273static int xl_list_tx_init_90xB(struct xl_softc *); 274static void xl_wait(struct xl_softc *); 275static void xl_mediacheck(struct xl_softc *); 276static void xl_choose_media(struct xl_softc *sc, int *media); 277static void xl_choose_xcvr(struct xl_softc *, int); 278static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 279#ifdef notdef 280static void xl_testpacket(struct xl_softc *); 281#endif 282 283static int xl_miibus_readreg(device_t, int, int); 284static int xl_miibus_writereg(device_t, int, int, int); 285static void xl_miibus_statchg(device_t); 286static void xl_miibus_mediainit(device_t); 287 288/* 289 * MII bit-bang glue 290 */ 291static uint32_t xl_mii_bitbang_read(device_t); 292static void xl_mii_bitbang_write(device_t, uint32_t); 293 294static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 295 xl_mii_bitbang_read, 296 xl_mii_bitbang_write, 297 { 298 XL_MII_DATA, /* MII_BIT_MDO */ 299 XL_MII_DATA, /* MII_BIT_MDI */ 300 XL_MII_CLK, /* MII_BIT_MDC */ 301 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 302 0, /* MII_BIT_DIR_PHY_HOST */ 303 } 304}; 305 306static device_method_t xl_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, xl_probe), 309 DEVMETHOD(device_attach, xl_attach), 310 DEVMETHOD(device_detach, xl_detach), 311 DEVMETHOD(device_shutdown, xl_shutdown), 312 DEVMETHOD(device_suspend, xl_suspend), 313 DEVMETHOD(device_resume, xl_resume), 314 315 /* MII interface */ 316 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 317 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 318 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 319 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 320 321 DEVMETHOD_END 322}; 323 324static driver_t xl_driver = { 325 "xl", 326 xl_methods, 327 sizeof(struct xl_softc) 328}; 329 330DRIVER_MODULE_ORDERED(xl, pci, xl_driver, NULL, NULL, SI_ORDER_ANY); 331DRIVER_MODULE(miibus, xl, miibus_driver, NULL, NULL); 332MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs, 333 nitems(xl_devs) - 1); 334 335static void 336xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 337{ 338 u_int32_t *paddr; 339 340 paddr = arg; 341 *paddr = segs->ds_addr; 342} 343 344/* 345 * Murphy's law says that it's possible the chip can wedge and 346 * the 'command in progress' bit may never clear. Hence, we wait 347 * only a finite amount of time to avoid getting caught in an 348 * infinite loop. Normally this delay routine would be a macro, 349 * but it isn't called during normal operation so we can afford 350 * to make it a function. Suppress warning when card gone. 351 */ 352static void 353xl_wait(struct xl_softc *sc) 354{ 355 int i; 356 357 for (i = 0; i < XL_TIMEOUT; i++) { 358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 359 break; 360 } 361 362 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 363 device_printf(sc->xl_dev, "command never completed!\n"); 364} 365 366/* 367 * MII access routines are provided for adapters with external 368 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 369 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 370 * Note: if you don't perform the MDIO operations just right, 371 * it's possible to end up with code that works correctly with 372 * some chips/CPUs/processor speeds/bus speeds/etc but not 373 * with others. 374 */ 375 376/* 377 * Read the MII serial port for the MII bit-bang module. 378 */ 379static uint32_t 380xl_mii_bitbang_read(device_t dev) 381{ 382 struct xl_softc *sc; 383 uint32_t val; 384 385 sc = device_get_softc(dev); 386 387 /* We're already in window 4. */ 388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 389 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 391 392 return (val); 393} 394 395/* 396 * Write the MII serial port for the MII bit-bang module. 397 */ 398static void 399xl_mii_bitbang_write(device_t dev, uint32_t val) 400{ 401 struct xl_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 /* We're already in window 4. */ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 407 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 409} 410 411static int 412xl_miibus_readreg(device_t dev, int phy, int reg) 413{ 414 struct xl_softc *sc; 415 416 sc = device_get_softc(dev); 417 418 /* Select the window 4. */ 419 XL_SEL_WIN(4); 420 421 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 422} 423 424static int 425xl_miibus_writereg(device_t dev, int phy, int reg, int data) 426{ 427 struct xl_softc *sc; 428 429 sc = device_get_softc(dev); 430 431 /* Select the window 4. */ 432 XL_SEL_WIN(4); 433 434 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 435 436 return (0); 437} 438 439static void 440xl_miibus_statchg(device_t dev) 441{ 442 struct xl_softc *sc; 443 struct mii_data *mii; 444 uint8_t macctl; 445 446 sc = device_get_softc(dev); 447 mii = device_get_softc(sc->xl_miibus); 448 449 xl_setcfg(sc); 450 451 /* Set ASIC's duplex mode to match the PHY. */ 452 XL_SEL_WIN(3); 453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 454 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 455 macctl |= XL_MACCTRL_DUPLEX; 456 if (sc->xl_type == XL_TYPE_905B) { 457 if ((IFM_OPTIONS(mii->mii_media_active) & 458 IFM_ETH_RXPAUSE) != 0) 459 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 460 else 461 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 462 } 463 } else { 464 macctl &= ~XL_MACCTRL_DUPLEX; 465 if (sc->xl_type == XL_TYPE_905B) 466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 467 } 468 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 469} 470 471/* 472 * Special support for the 3c905B-COMBO. This card has 10/100 support 473 * plus BNC and AUI ports. This means we will have both an miibus attached 474 * plus some non-MII media settings. In order to allow this, we have to 475 * add the extra media to the miibus's ifmedia struct, but we can't do 476 * that during xl_attach() because the miibus hasn't been attached yet. 477 * So instead, we wait until the miibus probe/attach is done, at which 478 * point we will get a callback telling is that it's safe to add our 479 * extra media. 480 */ 481static void 482xl_miibus_mediainit(device_t dev) 483{ 484 struct xl_softc *sc; 485 struct mii_data *mii; 486 struct ifmedia *ifm; 487 488 sc = device_get_softc(dev); 489 mii = device_get_softc(sc->xl_miibus); 490 ifm = &mii->mii_media; 491 492 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 493 /* 494 * Check for a 10baseFL board in disguise. 495 */ 496 if (sc->xl_type == XL_TYPE_905B && 497 sc->xl_media == XL_MEDIAOPT_10FL) { 498 if (bootverbose) 499 device_printf(sc->xl_dev, "found 10baseFL\n"); 500 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 501 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 502 NULL); 503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 504 ifmedia_add(ifm, 505 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 506 } else { 507 if (bootverbose) 508 device_printf(sc->xl_dev, "found AUI\n"); 509 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 510 } 511 } 512 513 if (sc->xl_media & XL_MEDIAOPT_BNC) { 514 if (bootverbose) 515 device_printf(sc->xl_dev, "found BNC\n"); 516 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 517 } 518} 519 520/* 521 * The EEPROM is slow: give it time to come ready after issuing 522 * it a command. 523 */ 524static int 525xl_eeprom_wait(struct xl_softc *sc) 526{ 527 int i; 528 529 for (i = 0; i < 100; i++) { 530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 531 DELAY(162); 532 else 533 break; 534 } 535 536 if (i == 100) { 537 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 538 return (1); 539 } 540 541 return (0); 542} 543 544/* 545 * Read a sequence of words from the EEPROM. Note that ethernet address 546 * data is stored in the EEPROM in network byte order. 547 */ 548static int 549xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 550{ 551 int err = 0, i; 552 u_int16_t word = 0, *ptr; 553 554#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 555#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 556 /* 557 * XXX: WARNING! DANGER! 558 * It's easy to accidentally overwrite the rom content! 559 * Note: the 3c575 uses 8bit EEPROM offsets. 560 */ 561 XL_SEL_WIN(0); 562 563 if (xl_eeprom_wait(sc)) 564 return (1); 565 566 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 567 off += 0x30; 568 569 for (i = 0; i < cnt; i++) { 570 if (sc->xl_flags & XL_FLAG_8BITROM) 571 CSR_WRITE_2(sc, XL_W0_EE_CMD, 572 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 573 else 574 CSR_WRITE_2(sc, XL_W0_EE_CMD, 575 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 576 err = xl_eeprom_wait(sc); 577 if (err) 578 break; 579 word = CSR_READ_2(sc, XL_W0_EE_DATA); 580 ptr = (u_int16_t *)(dest + (i * 2)); 581 if (swap) 582 *ptr = ntohs(word); 583 else 584 *ptr = word; 585 } 586 587 return (err ? 1 : 0); 588} 589 590static void 591xl_rxfilter(struct xl_softc *sc) 592{ 593 594 if (sc->xl_type == XL_TYPE_905B) 595 xl_rxfilter_90xB(sc); 596 else 597 xl_rxfilter_90x(sc); 598} 599 600/* 601 * NICs older than the 3c905B have only one multicast option, which 602 * is to enable reception of all multicast frames. 603 */ 604static u_int 605xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt) 606{ 607 uint8_t *rxfilt = arg; 608 609 *rxfilt |= XL_RXFILTER_ALLMULTI; 610 611 return (1); 612} 613 614static void 615xl_rxfilter_90x(struct xl_softc *sc) 616{ 617 if_t ifp; 618 u_int8_t rxfilt; 619 620 XL_LOCK_ASSERT(sc); 621 622 ifp = sc->xl_ifp; 623 624 XL_SEL_WIN(5); 625 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 626 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 627 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 628 629 /* Set the individual bit to receive frames for this host only. */ 630 rxfilt |= XL_RXFILTER_INDIVIDUAL; 631 /* Set capture broadcast bit to capture broadcast frames. */ 632 if (if_getflags(ifp) & IFF_BROADCAST) 633 rxfilt |= XL_RXFILTER_BROADCAST; 634 635 /* If we want promiscuous mode, set the allframes bit. */ 636 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 637 if (if_getflags(ifp) & IFF_PROMISC) 638 rxfilt |= XL_RXFILTER_ALLFRAMES; 639 if (if_getflags(ifp) & IFF_ALLMULTI) 640 rxfilt |= XL_RXFILTER_ALLMULTI; 641 } else 642 if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt); 643 644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 645 XL_SEL_WIN(7); 646} 647 648/* 649 * 3c905B adapters have a hash filter that we can program. 650 * Note: the 3c905B currently only supports a 64-bit 651 * hash table, which means we really only need 6 bits, 652 * but the manual indicates that future chip revisions 653 * will have a 256-bit hash table, hence the routine 654 * is set up to calculate 8 bits of position info in 655 * case we need it some day. 656 * Note II, The Sequel: _CURRENT_ versions of the 657 * 3c905B have a 256 bit hash table. This means we have 658 * to use all 8 bits regardless. On older cards, the 659 * upper 2 bits will be ignored. Grrrr.... 660 */ 661static u_int 662xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count) 663{ 664 struct xl_softc *sc = arg; 665 uint16_t h; 666 667 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 668 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 669 670 return (1); 671} 672 673static void 674xl_rxfilter_90xB(struct xl_softc *sc) 675{ 676 if_t ifp; 677 int i; 678 u_int8_t rxfilt; 679 680 XL_LOCK_ASSERT(sc); 681 682 ifp = sc->xl_ifp; 683 684 XL_SEL_WIN(5); 685 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 686 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 687 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 688 XL_RXFILTER_MULTIHASH); 689 690 /* Set the individual bit to receive frames for this host only. */ 691 rxfilt |= XL_RXFILTER_INDIVIDUAL; 692 /* Set capture broadcast bit to capture broadcast frames. */ 693 if (if_getflags(ifp) & IFF_BROADCAST) 694 rxfilt |= XL_RXFILTER_BROADCAST; 695 696 /* If we want promiscuous mode, set the allframes bit. */ 697 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 698 if (if_getflags(ifp) & IFF_PROMISC) 699 rxfilt |= XL_RXFILTER_ALLFRAMES; 700 if (if_getflags(ifp) & IFF_ALLMULTI) 701 rxfilt |= XL_RXFILTER_ALLMULTI; 702 } else { 703 /* First, zot all the existing hash bits. */ 704 for (i = 0; i < XL_HASHFILT_SIZE; i++) 705 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 706 707 /* Now program new ones. */ 708 if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0) 709 rxfilt |= XL_RXFILTER_MULTIHASH; 710 } 711 712 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 713 XL_SEL_WIN(7); 714} 715 716static void 717xl_setcfg(struct xl_softc *sc) 718{ 719 u_int32_t icfg; 720 721 /*XL_LOCK_ASSERT(sc);*/ 722 723 XL_SEL_WIN(3); 724 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 725 icfg &= ~XL_ICFG_CONNECTOR_MASK; 726 if (sc->xl_media & XL_MEDIAOPT_MII || 727 sc->xl_media & XL_MEDIAOPT_BT4) 728 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 729 if (sc->xl_media & XL_MEDIAOPT_BTX) 730 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 731 732 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 733 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 734} 735 736static void 737xl_setmode(struct xl_softc *sc, int media) 738{ 739 u_int32_t icfg; 740 u_int16_t mediastat; 741 char *pmsg = "", *dmsg = ""; 742 743 XL_LOCK_ASSERT(sc); 744 745 XL_SEL_WIN(4); 746 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 747 XL_SEL_WIN(3); 748 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 749 750 if (sc->xl_media & XL_MEDIAOPT_BT) { 751 if (IFM_SUBTYPE(media) == IFM_10_T) { 752 pmsg = "10baseT transceiver"; 753 sc->xl_xcvr = XL_XCVR_10BT; 754 icfg &= ~XL_ICFG_CONNECTOR_MASK; 755 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 756 mediastat |= XL_MEDIASTAT_LINKBEAT | 757 XL_MEDIASTAT_JABGUARD; 758 mediastat &= ~XL_MEDIASTAT_SQEENB; 759 } 760 } 761 762 if (sc->xl_media & XL_MEDIAOPT_BFX) { 763 if (IFM_SUBTYPE(media) == IFM_100_FX) { 764 pmsg = "100baseFX port"; 765 sc->xl_xcvr = XL_XCVR_100BFX; 766 icfg &= ~XL_ICFG_CONNECTOR_MASK; 767 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 768 mediastat |= XL_MEDIASTAT_LINKBEAT; 769 mediastat &= ~XL_MEDIASTAT_SQEENB; 770 } 771 } 772 773 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 774 if (IFM_SUBTYPE(media) == IFM_10_5) { 775 pmsg = "AUI port"; 776 sc->xl_xcvr = XL_XCVR_AUI; 777 icfg &= ~XL_ICFG_CONNECTOR_MASK; 778 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 779 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 780 XL_MEDIASTAT_JABGUARD); 781 mediastat |= ~XL_MEDIASTAT_SQEENB; 782 } 783 if (IFM_SUBTYPE(media) == IFM_10_FL) { 784 pmsg = "10baseFL transceiver"; 785 sc->xl_xcvr = XL_XCVR_AUI; 786 icfg &= ~XL_ICFG_CONNECTOR_MASK; 787 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 788 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 789 XL_MEDIASTAT_JABGUARD); 790 mediastat |= ~XL_MEDIASTAT_SQEENB; 791 } 792 } 793 794 if (sc->xl_media & XL_MEDIAOPT_BNC) { 795 if (IFM_SUBTYPE(media) == IFM_10_2) { 796 pmsg = "AUI port"; 797 sc->xl_xcvr = XL_XCVR_COAX; 798 icfg &= ~XL_ICFG_CONNECTOR_MASK; 799 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 800 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 801 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 802 } 803 } 804 805 if ((media & IFM_GMASK) == IFM_FDX || 806 IFM_SUBTYPE(media) == IFM_100_FX) { 807 dmsg = "full"; 808 XL_SEL_WIN(3); 809 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 810 } else { 811 dmsg = "half"; 812 XL_SEL_WIN(3); 813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 814 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 815 } 816 817 if (IFM_SUBTYPE(media) == IFM_10_2) 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 819 else 820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 821 822 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 823 XL_SEL_WIN(4); 824 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 825 826 DELAY(800); 827 XL_SEL_WIN(7); 828 829 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 830} 831 832static void 833xl_reset(struct xl_softc *sc) 834{ 835 int i; 836 837 XL_LOCK_ASSERT(sc); 838 839 XL_SEL_WIN(0); 840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 841 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 842 XL_RESETOPT_DISADVFD:0)); 843 844 /* 845 * If we're using memory mapped register mode, pause briefly 846 * after issuing the reset command before trying to access any 847 * other registers. With my 3c575C CardBus card, failing to do 848 * this results in the system locking up while trying to poll 849 * the command busy bit in the status register. 850 */ 851 if (sc->xl_flags & XL_FLAG_USE_MMIO) 852 DELAY(100000); 853 854 for (i = 0; i < XL_TIMEOUT; i++) { 855 DELAY(10); 856 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 857 break; 858 } 859 860 if (i == XL_TIMEOUT) 861 device_printf(sc->xl_dev, "reset didn't complete\n"); 862 863 /* Reset TX and RX. */ 864 /* Note: the RX reset takes an absurd amount of time 865 * on newer versions of the Tornado chips such as those 866 * on the 3c905CX and newer 3c908C cards. We wait an 867 * extra amount of time so that xl_wait() doesn't complain 868 * and annoy the users. 869 */ 870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 871 DELAY(100000); 872 xl_wait(sc); 873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 874 xl_wait(sc); 875 876 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 877 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 878 XL_SEL_WIN(2); 879 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 880 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 881 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 882 XL_RESETOPT_INVERT_LED : 0) | 883 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 884 XL_RESETOPT_INVERT_MII : 0)); 885 } 886 887 /* Wait a little while for the chip to get its brains in order. */ 888 DELAY(100000); 889} 890 891/* 892 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 893 * IDs against our list and return a device name if we find a match. 894 */ 895static int 896xl_probe(device_t dev) 897{ 898 const struct xl_type *t; 899 900 t = xl_devs; 901 902 while (t->xl_name != NULL) { 903 if ((pci_get_vendor(dev) == t->xl_vid) && 904 (pci_get_device(dev) == t->xl_did)) { 905 device_set_desc(dev, t->xl_name); 906 return (BUS_PROBE_DEFAULT); 907 } 908 t++; 909 } 910 911 return (ENXIO); 912} 913 914/* 915 * This routine is a kludge to work around possible hardware faults 916 * or manufacturing defects that can cause the media options register 917 * (or reset options register, as it's called for the first generation 918 * 3c90x adapters) to return an incorrect result. I have encountered 919 * one Dell Latitude laptop docking station with an integrated 3c905-TX 920 * which doesn't have any of the 'mediaopt' bits set. This screws up 921 * the attach routine pretty badly because it doesn't know what media 922 * to look for. If we find ourselves in this predicament, this routine 923 * will try to guess the media options values and warn the user of a 924 * possible manufacturing defect with his adapter/system/whatever. 925 */ 926static void 927xl_mediacheck(struct xl_softc *sc) 928{ 929 930 /* 931 * If some of the media options bits are set, assume they are 932 * correct. If not, try to figure it out down below. 933 * XXX I should check for 10baseFL, but I don't have an adapter 934 * to test with. 935 */ 936 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 937 /* 938 * Check the XCVR value. If it's not in the normal range 939 * of values, we need to fake it up here. 940 */ 941 if (sc->xl_xcvr <= XL_XCVR_AUTO) 942 return; 943 else { 944 device_printf(sc->xl_dev, 945 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 946 device_printf(sc->xl_dev, 947 "choosing new default based on card type\n"); 948 } 949 } else { 950 if (sc->xl_type == XL_TYPE_905B && 951 sc->xl_media & XL_MEDIAOPT_10FL) 952 return; 953 device_printf(sc->xl_dev, 954"WARNING: no media options bits set in the media options register!!\n"); 955 device_printf(sc->xl_dev, 956"this could be a manufacturing defect in your adapter or system\n"); 957 device_printf(sc->xl_dev, 958"attempting to guess media type; you should probably consult your vendor\n"); 959 } 960 961 xl_choose_xcvr(sc, 1); 962} 963 964static void 965xl_choose_xcvr(struct xl_softc *sc, int verbose) 966{ 967 u_int16_t devid; 968 969 /* 970 * Read the device ID from the EEPROM. 971 * This is what's loaded into the PCI device ID register, so it has 972 * to be correct otherwise we wouldn't have gotten this far. 973 */ 974 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 975 976 switch (devid) { 977 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 978 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 979 sc->xl_media = XL_MEDIAOPT_BT; 980 sc->xl_xcvr = XL_XCVR_10BT; 981 if (verbose) 982 device_printf(sc->xl_dev, 983 "guessing 10BaseT transceiver\n"); 984 break; 985 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 986 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 987 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 988 sc->xl_xcvr = XL_XCVR_10BT; 989 if (verbose) 990 device_printf(sc->xl_dev, 991 "guessing COMBO (AUI/BNC/TP)\n"); 992 break; 993 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 994 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 995 sc->xl_xcvr = XL_XCVR_10BT; 996 if (verbose) 997 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 998 break; 999 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1000 sc->xl_media = XL_MEDIAOPT_10FL; 1001 sc->xl_xcvr = XL_XCVR_AUI; 1002 if (verbose) 1003 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1004 break; 1005 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1006 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1007 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1008 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1009 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1010 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1011 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1012 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1013 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1014 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1015 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1016 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1017 sc->xl_media = XL_MEDIAOPT_MII; 1018 sc->xl_xcvr = XL_XCVR_MII; 1019 if (verbose) 1020 device_printf(sc->xl_dev, "guessing MII\n"); 1021 break; 1022 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1023 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1024 sc->xl_media = XL_MEDIAOPT_BT4; 1025 sc->xl_xcvr = XL_XCVR_MII; 1026 if (verbose) 1027 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1028 break; 1029 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1030 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1031 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1032 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1033 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1034 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1035 sc->xl_media = XL_MEDIAOPT_BTX; 1036 sc->xl_xcvr = XL_XCVR_AUTO; 1037 if (verbose) 1038 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1039 break; 1040 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1041 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1042 sc->xl_xcvr = XL_XCVR_AUTO; 1043 if (verbose) 1044 device_printf(sc->xl_dev, 1045 "guessing 10/100 plus BNC/AUI\n"); 1046 break; 1047 default: 1048 device_printf(sc->xl_dev, 1049 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1050 sc->xl_media = XL_MEDIAOPT_BT; 1051 break; 1052 } 1053} 1054 1055/* 1056 * Attach the interface. Allocate softc structures, do ifmedia 1057 * setup and ethernet/BPF attach. 1058 */ 1059static int 1060xl_attach(device_t dev) 1061{ 1062 u_char eaddr[ETHER_ADDR_LEN]; 1063 u_int16_t sinfo2, xcvr[2]; 1064 struct xl_softc *sc; 1065 if_t ifp; 1066 int media, pmcap; 1067 int error = 0, phy, rid, res; 1068 uint16_t did; 1069 1070 sc = device_get_softc(dev); 1071 sc->xl_dev = dev; 1072 1073 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1074 MTX_DEF); 1075 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1076 1077 did = pci_get_device(dev); 1078 1079 sc->xl_flags = 0; 1080 if (did == TC_DEVICEID_HURRICANE_555) 1081 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1082 if (did == TC_DEVICEID_HURRICANE_556 || 1083 did == TC_DEVICEID_HURRICANE_556B) 1084 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1085 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1086 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1087 if (did == TC_DEVICEID_HURRICANE_555 || 1088 did == TC_DEVICEID_HURRICANE_556) 1089 sc->xl_flags |= XL_FLAG_8BITROM; 1090 if (did == TC_DEVICEID_HURRICANE_556B) 1091 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1092 1093 if (did == TC_DEVICEID_HURRICANE_575B || 1094 did == TC_DEVICEID_HURRICANE_575C || 1095 did == TC_DEVICEID_HURRICANE_656B || 1096 did == TC_DEVICEID_TORNADO_656C) 1097 sc->xl_flags |= XL_FLAG_FUNCREG; 1098 if (did == TC_DEVICEID_HURRICANE_575A || 1099 did == TC_DEVICEID_HURRICANE_575B || 1100 did == TC_DEVICEID_HURRICANE_575C || 1101 did == TC_DEVICEID_HURRICANE_656B || 1102 did == TC_DEVICEID_TORNADO_656C) 1103 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1104 XL_FLAG_8BITROM; 1105 if (did == TC_DEVICEID_HURRICANE_656) 1106 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1107 if (did == TC_DEVICEID_HURRICANE_575B) 1108 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1109 if (did == TC_DEVICEID_HURRICANE_575C) 1110 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1111 if (did == TC_DEVICEID_TORNADO_656C) 1112 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1113 if (did == TC_DEVICEID_HURRICANE_656 || 1114 did == TC_DEVICEID_HURRICANE_656B) 1115 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1116 XL_FLAG_INVERT_LED_PWR; 1117 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1118 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1119 sc->xl_flags |= XL_FLAG_PHYOK; 1120 1121 switch (did) { 1122 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1123 case TC_DEVICEID_HURRICANE_575A: 1124 case TC_DEVICEID_HURRICANE_575B: 1125 case TC_DEVICEID_HURRICANE_575C: 1126 sc->xl_flags |= XL_FLAG_NO_MMIO; 1127 break; 1128 default: 1129 break; 1130 } 1131 1132 /* 1133 * Map control/status registers. 1134 */ 1135 pci_enable_busmaster(dev); 1136 1137 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1138 rid = XL_PCI_LOMEM; 1139 res = SYS_RES_MEMORY; 1140 1141 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1142 } 1143 1144 if (sc->xl_res != NULL) { 1145 sc->xl_flags |= XL_FLAG_USE_MMIO; 1146 if (bootverbose) 1147 device_printf(dev, "using memory mapped I/O\n"); 1148 } else { 1149 rid = XL_PCI_LOIO; 1150 res = SYS_RES_IOPORT; 1151 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1152 if (sc->xl_res == NULL) { 1153 device_printf(dev, "couldn't map ports/memory\n"); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 if (bootverbose) 1158 device_printf(dev, "using port I/O\n"); 1159 } 1160 1161 sc->xl_btag = rman_get_bustag(sc->xl_res); 1162 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1163 1164 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1165 rid = XL_PCI_FUNCMEM; 1166 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1167 RF_ACTIVE); 1168 1169 if (sc->xl_fres == NULL) { 1170 device_printf(dev, "couldn't map funcreg memory\n"); 1171 error = ENXIO; 1172 goto fail; 1173 } 1174 1175 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1176 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1177 } 1178 1179 /* Allocate interrupt */ 1180 rid = 0; 1181 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1182 RF_SHAREABLE | RF_ACTIVE); 1183 if (sc->xl_irq == NULL) { 1184 device_printf(dev, "couldn't map interrupt\n"); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 /* Initialize interface name. */ 1190 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1191 if (ifp == NULL) { 1192 device_printf(dev, "can not if_alloc()\n"); 1193 error = ENOSPC; 1194 goto fail; 1195 } 1196 if_setsoftc(ifp, sc); 1197 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1198 1199 /* Reset the adapter. */ 1200 XL_LOCK(sc); 1201 xl_reset(sc); 1202 XL_UNLOCK(sc); 1203 1204 /* 1205 * Get station address from the EEPROM. 1206 */ 1207 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1208 device_printf(dev, "failed to read station address\n"); 1209 error = ENXIO; 1210 goto fail; 1211 } 1212 1213 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1214 NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1215 1216 /* 1217 * Now allocate a tag for the DMA descriptor lists and a chunk 1218 * of DMA-able memory based on the tag. Also obtain the DMA 1219 * addresses of the RX and TX ring, which we'll need later. 1220 * All of our lists are allocated as a contiguous block 1221 * of memory. 1222 */ 1223 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1224 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1225 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1226 &sc->xl_ldata.xl_rx_tag); 1227 if (error) { 1228 device_printf(dev, "failed to allocate rx dma tag\n"); 1229 goto fail; 1230 } 1231 1232 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1233 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1234 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1235 if (error) { 1236 device_printf(dev, "no memory for rx list buffers!\n"); 1237 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1238 sc->xl_ldata.xl_rx_tag = NULL; 1239 goto fail; 1240 } 1241 1242 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1243 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1244 XL_RX_LIST_SZ, xl_dma_map_addr, 1245 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1246 if (error) { 1247 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1248 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1249 sc->xl_ldata.xl_rx_dmamap); 1250 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1251 sc->xl_ldata.xl_rx_tag = NULL; 1252 goto fail; 1253 } 1254 1255 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1256 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1257 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1258 &sc->xl_ldata.xl_tx_tag); 1259 if (error) { 1260 device_printf(dev, "failed to allocate tx dma tag\n"); 1261 goto fail; 1262 } 1263 1264 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1265 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1266 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1267 if (error) { 1268 device_printf(dev, "no memory for list buffers!\n"); 1269 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1270 sc->xl_ldata.xl_tx_tag = NULL; 1271 goto fail; 1272 } 1273 1274 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1275 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1276 XL_TX_LIST_SZ, xl_dma_map_addr, 1277 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1278 if (error) { 1279 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1280 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1281 sc->xl_ldata.xl_tx_dmamap); 1282 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1283 sc->xl_ldata.xl_tx_tag = NULL; 1284 goto fail; 1285 } 1286 1287 /* 1288 * Allocate a DMA tag for the mapping of mbufs. 1289 */ 1290 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1291 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1292 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1293 NULL, &sc->xl_mtag); 1294 if (error) { 1295 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1296 goto fail; 1297 } 1298 1299 /* We need a spare DMA map for the RX ring. */ 1300 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1301 if (error) 1302 goto fail; 1303 1304 /* 1305 * Figure out the card type. 3c905B adapters have the 1306 * 'supportsNoTxLength' bit set in the capabilities 1307 * word in the EEPROM. 1308 * Note: my 3c575C CardBus card lies. It returns a value 1309 * of 0x1578 for its capabilities word, which is somewhat 1310 * nonsensical. Another way to distinguish a 3c90x chip 1311 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1312 * bit. This will only be set for 3c90x boomerage chips. 1313 */ 1314 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1315 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1316 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1317 sc->xl_type = XL_TYPE_905B; 1318 else 1319 sc->xl_type = XL_TYPE_90X; 1320 1321 /* Check availability of WOL. */ 1322 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1323 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1324 sc->xl_pmcap = pmcap; 1325 sc->xl_flags |= XL_FLAG_WOL; 1326 sinfo2 = 0; 1327 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1328 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1329 device_printf(dev, 1330 "No auxiliary remote wakeup connector!\n"); 1331 } 1332 1333 /* Set the TX start threshold for best performance. */ 1334 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1335 1336 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1337 if_setioctlfn(ifp, xl_ioctl); 1338 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1339 if (sc->xl_type == XL_TYPE_905B) { 1340 if_sethwassist(ifp, XL905B_CSUM_FEATURES); 1341#ifdef XL905B_TXCSUM_BROKEN 1342 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1343#else 1344 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 1345#endif 1346 } 1347 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1348 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1349 if_setcapenable(ifp, if_getcapabilities(ifp)); 1350#ifdef DEVICE_POLLING 1351 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1352#endif 1353 if_setstartfn(ifp, xl_start); 1354 if_setinitfn(ifp, xl_init); 1355 if_setsendqlen(ifp, XL_TX_LIST_CNT - 1); 1356 if_setsendqready(ifp); 1357 1358 /* 1359 * Now we have to see what sort of media we have. 1360 * This includes probing for an MII interace and a 1361 * possible PHY. 1362 */ 1363 XL_SEL_WIN(3); 1364 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1365 if (bootverbose) 1366 device_printf(dev, "media options word: %x\n", sc->xl_media); 1367 1368 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1369 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1370 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1371 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1372 1373 xl_mediacheck(sc); 1374 1375 if (sc->xl_media & XL_MEDIAOPT_MII || 1376 sc->xl_media & XL_MEDIAOPT_BTX || 1377 sc->xl_media & XL_MEDIAOPT_BT4) { 1378 if (bootverbose) 1379 device_printf(dev, "found MII/AUTO\n"); 1380 xl_setcfg(sc); 1381 /* 1382 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1383 * This is to guard against problems with certain 3Com ASIC 1384 * revisions that incorrectly map the internal transceiver 1385 * control registers at all MII addresses. 1386 */ 1387 phy = MII_PHY_ANY; 1388 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1389 phy = 24; 1390 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1391 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1392 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1393 if (error != 0) { 1394 device_printf(dev, "attaching PHYs failed\n"); 1395 goto fail; 1396 } 1397 goto done; 1398 } 1399 1400 /* 1401 * Sanity check. If the user has selected "auto" and this isn't 1402 * a 10/100 card of some kind, we need to force the transceiver 1403 * type to something sane. 1404 */ 1405 if (sc->xl_xcvr == XL_XCVR_AUTO) 1406 xl_choose_xcvr(sc, bootverbose); 1407 1408 /* 1409 * Do ifmedia setup. 1410 */ 1411 if (sc->xl_media & XL_MEDIAOPT_BT) { 1412 if (bootverbose) 1413 device_printf(dev, "found 10baseT\n"); 1414 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1415 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1416 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1417 ifmedia_add(&sc->ifmedia, 1418 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1419 } 1420 1421 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1422 /* 1423 * Check for a 10baseFL board in disguise. 1424 */ 1425 if (sc->xl_type == XL_TYPE_905B && 1426 sc->xl_media == XL_MEDIAOPT_10FL) { 1427 if (bootverbose) 1428 device_printf(dev, "found 10baseFL\n"); 1429 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1430 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1431 0, NULL); 1432 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1433 ifmedia_add(&sc->ifmedia, 1434 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1435 } else { 1436 if (bootverbose) 1437 device_printf(dev, "found AUI\n"); 1438 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1439 } 1440 } 1441 1442 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1443 if (bootverbose) 1444 device_printf(dev, "found BNC\n"); 1445 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1446 } 1447 1448 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1449 if (bootverbose) 1450 device_printf(dev, "found 100baseFX\n"); 1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1452 } 1453 1454 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1455 xl_choose_media(sc, &media); 1456 1457 if (sc->xl_miibus == NULL) 1458 ifmedia_set(&sc->ifmedia, media); 1459 1460done: 1461 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1462 XL_SEL_WIN(0); 1463 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1464 } 1465 1466 /* 1467 * Call MI attach routine. 1468 */ 1469 ether_ifattach(ifp, eaddr); 1470 1471 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1472 NULL, xl_intr, sc, &sc->xl_intrhand); 1473 if (error) { 1474 device_printf(dev, "couldn't set up irq\n"); 1475 ether_ifdetach(ifp); 1476 goto fail; 1477 } 1478 1479fail: 1480 if (error) 1481 xl_detach(dev); 1482 1483 return (error); 1484} 1485 1486/* 1487 * Choose a default media. 1488 * XXX This is a leaf function only called by xl_attach() and 1489 * acquires/releases the non-recursible driver mutex to 1490 * satisfy lock assertions. 1491 */ 1492static void 1493xl_choose_media(struct xl_softc *sc, int *media) 1494{ 1495 1496 XL_LOCK(sc); 1497 1498 switch (sc->xl_xcvr) { 1499 case XL_XCVR_10BT: 1500 *media = IFM_ETHER|IFM_10_T; 1501 xl_setmode(sc, *media); 1502 break; 1503 case XL_XCVR_AUI: 1504 if (sc->xl_type == XL_TYPE_905B && 1505 sc->xl_media == XL_MEDIAOPT_10FL) { 1506 *media = IFM_ETHER|IFM_10_FL; 1507 xl_setmode(sc, *media); 1508 } else { 1509 *media = IFM_ETHER|IFM_10_5; 1510 xl_setmode(sc, *media); 1511 } 1512 break; 1513 case XL_XCVR_COAX: 1514 *media = IFM_ETHER|IFM_10_2; 1515 xl_setmode(sc, *media); 1516 break; 1517 case XL_XCVR_AUTO: 1518 case XL_XCVR_100BTX: 1519 case XL_XCVR_MII: 1520 /* Chosen by miibus */ 1521 break; 1522 case XL_XCVR_100BFX: 1523 *media = IFM_ETHER|IFM_100_FX; 1524 break; 1525 default: 1526 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1527 sc->xl_xcvr); 1528 /* 1529 * This will probably be wrong, but it prevents 1530 * the ifmedia code from panicking. 1531 */ 1532 *media = IFM_ETHER|IFM_10_T; 1533 break; 1534 } 1535 1536 XL_UNLOCK(sc); 1537} 1538 1539/* 1540 * Shutdown hardware and free up resources. This can be called any 1541 * time after the mutex has been initialized. It is called in both 1542 * the error case in attach and the normal detach case so it needs 1543 * to be careful about only freeing resources that have actually been 1544 * allocated. 1545 */ 1546static int 1547xl_detach(device_t dev) 1548{ 1549 struct xl_softc *sc; 1550 if_t ifp; 1551 int rid, res; 1552 1553 sc = device_get_softc(dev); 1554 ifp = sc->xl_ifp; 1555 1556 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1557 1558#ifdef DEVICE_POLLING 1559 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING) 1560 ether_poll_deregister(ifp); 1561#endif 1562 1563 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1564 rid = XL_PCI_LOMEM; 1565 res = SYS_RES_MEMORY; 1566 } else { 1567 rid = XL_PCI_LOIO; 1568 res = SYS_RES_IOPORT; 1569 } 1570 1571 /* These should only be active if attach succeeded */ 1572 if (device_is_attached(dev)) { 1573 XL_LOCK(sc); 1574 xl_stop(sc); 1575 XL_UNLOCK(sc); 1576 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1577 callout_drain(&sc->xl_tick_callout); 1578 ether_ifdetach(ifp); 1579 } 1580 if (sc->xl_miibus) 1581 device_delete_child(dev, sc->xl_miibus); 1582 bus_generic_detach(dev); 1583 ifmedia_removeall(&sc->ifmedia); 1584 1585 if (sc->xl_intrhand) 1586 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1587 if (sc->xl_irq) 1588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1589 if (sc->xl_fres != NULL) 1590 bus_release_resource(dev, SYS_RES_MEMORY, 1591 XL_PCI_FUNCMEM, sc->xl_fres); 1592 if (sc->xl_res) 1593 bus_release_resource(dev, res, rid, sc->xl_res); 1594 1595 if (ifp) 1596 if_free(ifp); 1597 1598 if (sc->xl_mtag) { 1599 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1600 bus_dma_tag_destroy(sc->xl_mtag); 1601 } 1602 if (sc->xl_ldata.xl_rx_tag) { 1603 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1604 sc->xl_ldata.xl_rx_dmamap); 1605 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1606 sc->xl_ldata.xl_rx_dmamap); 1607 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1608 } 1609 if (sc->xl_ldata.xl_tx_tag) { 1610 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1611 sc->xl_ldata.xl_tx_dmamap); 1612 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1613 sc->xl_ldata.xl_tx_dmamap); 1614 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1615 } 1616 1617 mtx_destroy(&sc->xl_mtx); 1618 1619 return (0); 1620} 1621 1622/* 1623 * Initialize the transmit descriptors. 1624 */ 1625static int 1626xl_list_tx_init(struct xl_softc *sc) 1627{ 1628 struct xl_chain_data *cd; 1629 struct xl_list_data *ld; 1630 int error, i; 1631 1632 XL_LOCK_ASSERT(sc); 1633 1634 cd = &sc->xl_cdata; 1635 ld = &sc->xl_ldata; 1636 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1637 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1638 error = bus_dmamap_create(sc->xl_mtag, 0, 1639 &cd->xl_tx_chain[i].xl_map); 1640 if (error) 1641 return (error); 1642 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1643 i * sizeof(struct xl_list); 1644 if (i == (XL_TX_LIST_CNT - 1)) 1645 cd->xl_tx_chain[i].xl_next = NULL; 1646 else 1647 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1648 } 1649 1650 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1651 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1652 1653 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1654 return (0); 1655} 1656 1657/* 1658 * Initialize the transmit descriptors. 1659 */ 1660static int 1661xl_list_tx_init_90xB(struct xl_softc *sc) 1662{ 1663 struct xl_chain_data *cd; 1664 struct xl_list_data *ld; 1665 int error, i; 1666 1667 XL_LOCK_ASSERT(sc); 1668 1669 cd = &sc->xl_cdata; 1670 ld = &sc->xl_ldata; 1671 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1672 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1673 error = bus_dmamap_create(sc->xl_mtag, 0, 1674 &cd->xl_tx_chain[i].xl_map); 1675 if (error) 1676 return (error); 1677 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1678 i * sizeof(struct xl_list); 1679 if (i == (XL_TX_LIST_CNT - 1)) 1680 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1681 else 1682 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1683 if (i == 0) 1684 cd->xl_tx_chain[i].xl_prev = 1685 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1686 else 1687 cd->xl_tx_chain[i].xl_prev = 1688 &cd->xl_tx_chain[i - 1]; 1689 } 1690 1691 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1692 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1693 1694 cd->xl_tx_prod = 1; 1695 cd->xl_tx_cons = 1; 1696 cd->xl_tx_cnt = 0; 1697 1698 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1699 return (0); 1700} 1701 1702/* 1703 * Initialize the RX descriptors and allocate mbufs for them. Note that 1704 * we arrange the descriptors in a closed ring, so that the last descriptor 1705 * points back to the first. 1706 */ 1707static int 1708xl_list_rx_init(struct xl_softc *sc) 1709{ 1710 struct xl_chain_data *cd; 1711 struct xl_list_data *ld; 1712 int error, i, next; 1713 u_int32_t nextptr; 1714 1715 XL_LOCK_ASSERT(sc); 1716 1717 cd = &sc->xl_cdata; 1718 ld = &sc->xl_ldata; 1719 1720 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1721 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1722 error = bus_dmamap_create(sc->xl_mtag, 0, 1723 &cd->xl_rx_chain[i].xl_map); 1724 if (error) 1725 return (error); 1726 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1727 if (error) 1728 return (error); 1729 if (i == (XL_RX_LIST_CNT - 1)) 1730 next = 0; 1731 else 1732 next = i + 1; 1733 nextptr = ld->xl_rx_dmaaddr + 1734 next * sizeof(struct xl_list_onefrag); 1735 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1736 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1737 } 1738 1739 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1740 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1741 1742 return (0); 1743} 1744 1745/* 1746 * Initialize an RX descriptor and attach an MBUF cluster. 1747 * If we fail to do so, we need to leave the old mbuf and 1748 * the old DMA map untouched so that it can be reused. 1749 */ 1750static int 1751xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1752{ 1753 struct mbuf *m_new = NULL; 1754 bus_dmamap_t map; 1755 bus_dma_segment_t segs[1]; 1756 int error, nseg; 1757 1758 XL_LOCK_ASSERT(sc); 1759 1760 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1761 if (m_new == NULL) 1762 return (ENOBUFS); 1763 1764 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1765 1766 /* Force longword alignment for packet payload. */ 1767 m_adj(m_new, ETHER_ALIGN); 1768 1769 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1770 segs, &nseg, BUS_DMA_NOWAIT); 1771 if (error) { 1772 m_freem(m_new); 1773 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1774 error); 1775 return (error); 1776 } 1777 KASSERT(nseg == 1, 1778 ("%s: too many DMA segments (%d)", __func__, nseg)); 1779 1780 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1781 map = c->xl_map; 1782 c->xl_map = sc->xl_tmpmap; 1783 sc->xl_tmpmap = map; 1784 c->xl_mbuf = m_new; 1785 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1786 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1787 c->xl_ptr->xl_status = 0; 1788 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1789 return (0); 1790} 1791 1792static int 1793xl_rx_resync(struct xl_softc *sc) 1794{ 1795 struct xl_chain_onefrag *pos; 1796 int i; 1797 1798 XL_LOCK_ASSERT(sc); 1799 1800 pos = sc->xl_cdata.xl_rx_head; 1801 1802 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1803 if (pos->xl_ptr->xl_status) 1804 break; 1805 pos = pos->xl_next; 1806 } 1807 1808 if (i == XL_RX_LIST_CNT) 1809 return (0); 1810 1811 sc->xl_cdata.xl_rx_head = pos; 1812 1813 return (EAGAIN); 1814} 1815 1816/* 1817 * A frame has been uploaded: pass the resulting mbuf chain up to 1818 * the higher level protocols. 1819 */ 1820static int 1821xl_rxeof(struct xl_softc *sc) 1822{ 1823 struct mbuf *m; 1824 if_t ifp = sc->xl_ifp; 1825 struct xl_chain_onefrag *cur_rx; 1826 int total_len; 1827 int rx_npkts = 0; 1828 u_int32_t rxstat; 1829 1830 XL_LOCK_ASSERT(sc); 1831again: 1832 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1833 BUS_DMASYNC_POSTREAD); 1834 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1835#ifdef DEVICE_POLLING 1836 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1837 if (sc->rxcycles <= 0) 1838 break; 1839 sc->rxcycles--; 1840 } 1841#endif 1842 cur_rx = sc->xl_cdata.xl_rx_head; 1843 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1844 total_len = rxstat & XL_RXSTAT_LENMASK; 1845 rx_npkts++; 1846 1847 /* 1848 * Since we have told the chip to allow large frames, 1849 * we need to trap giant frame errors in software. We allow 1850 * a little more than the normal frame size to account for 1851 * frames with VLAN tags. 1852 */ 1853 if (total_len > XL_MAX_FRAMELEN) 1854 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1855 1856 /* 1857 * If an error occurs, update stats, clear the 1858 * status word and leave the mbuf cluster in place: 1859 * it should simply get re-used next time this descriptor 1860 * comes up in the ring. 1861 */ 1862 if (rxstat & XL_RXSTAT_UP_ERROR) { 1863 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1864 cur_rx->xl_ptr->xl_status = 0; 1865 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1866 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1867 continue; 1868 } 1869 1870 /* 1871 * If the error bit was not set, the upload complete 1872 * bit should be set which means we have a valid packet. 1873 * If not, something truly strange has happened. 1874 */ 1875 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1876 device_printf(sc->xl_dev, 1877 "bad receive status -- packet dropped\n"); 1878 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1879 cur_rx->xl_ptr->xl_status = 0; 1880 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1881 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1882 continue; 1883 } 1884 1885 /* No errors; receive the packet. */ 1886 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1887 BUS_DMASYNC_POSTREAD); 1888 m = cur_rx->xl_mbuf; 1889 1890 /* 1891 * Try to conjure up a new mbuf cluster. If that 1892 * fails, it means we have an out of memory condition and 1893 * should leave the buffer in place and continue. This will 1894 * result in a lost packet, but there's little else we 1895 * can do in this situation. 1896 */ 1897 if (xl_newbuf(sc, cur_rx)) { 1898 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1899 cur_rx->xl_ptr->xl_status = 0; 1900 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1901 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1902 continue; 1903 } 1904 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1905 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1906 1907 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1908 m->m_pkthdr.rcvif = ifp; 1909 m->m_pkthdr.len = m->m_len = total_len; 1910 1911 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 1912 /* Do IP checksum checking. */ 1913 if (rxstat & XL_RXSTAT_IPCKOK) 1914 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1915 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1916 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1917 if ((rxstat & XL_RXSTAT_TCPCOK && 1918 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1919 (rxstat & XL_RXSTAT_UDPCKOK && 1920 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1921 m->m_pkthdr.csum_flags |= 1922 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1923 m->m_pkthdr.csum_data = 0xffff; 1924 } 1925 } 1926 1927 XL_UNLOCK(sc); 1928 if_input(ifp, m); 1929 XL_LOCK(sc); 1930 1931 /* 1932 * If we are running from the taskqueue, the interface 1933 * might have been stopped while we were passing the last 1934 * packet up the network stack. 1935 */ 1936 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 1937 return (rx_npkts); 1938 } 1939 1940 /* 1941 * Handle the 'end of channel' condition. When the upload 1942 * engine hits the end of the RX ring, it will stall. This 1943 * is our cue to flush the RX ring, reload the uplist pointer 1944 * register and unstall the engine. 1945 * XXX This is actually a little goofy. With the ThunderLAN 1946 * chip, you get an interrupt when the receiver hits the end 1947 * of the receive ring, which tells you exactly when you 1948 * you need to reload the ring pointer. Here we have to 1949 * fake it. I'm mad at myself for not being clever enough 1950 * to avoid the use of a goto here. 1951 */ 1952 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1953 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1954 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1955 xl_wait(sc); 1956 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1957 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1959 goto again; 1960 } 1961 return (rx_npkts); 1962} 1963 1964/* 1965 * Taskqueue wrapper for xl_rxeof(). 1966 */ 1967static void 1968xl_rxeof_task(void *arg, int pending) 1969{ 1970 struct xl_softc *sc = (struct xl_softc *)arg; 1971 1972 XL_LOCK(sc); 1973 if (if_getdrvflags(sc->xl_ifp) & IFF_DRV_RUNNING) 1974 xl_rxeof(sc); 1975 XL_UNLOCK(sc); 1976} 1977 1978/* 1979 * A frame was downloaded to the chip. It's safe for us to clean up 1980 * the list buffers. 1981 */ 1982static void 1983xl_txeof(struct xl_softc *sc) 1984{ 1985 struct xl_chain *cur_tx; 1986 if_t ifp = sc->xl_ifp; 1987 1988 XL_LOCK_ASSERT(sc); 1989 1990 /* 1991 * Go through our tx list and free mbufs for those 1992 * frames that have been uploaded. Note: the 3c905B 1993 * sets a special bit in the status word to let us 1994 * know that a frame has been downloaded, but the 1995 * original 3c900/3c905 adapters don't do that. 1996 * Consequently, we have to use a different test if 1997 * xl_type != XL_TYPE_905B. 1998 */ 1999 while (sc->xl_cdata.xl_tx_head != NULL) { 2000 cur_tx = sc->xl_cdata.xl_tx_head; 2001 2002 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2003 break; 2004 2005 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2006 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2007 BUS_DMASYNC_POSTWRITE); 2008 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2009 m_freem(cur_tx->xl_mbuf); 2010 cur_tx->xl_mbuf = NULL; 2011 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2012 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2013 2014 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2015 sc->xl_cdata.xl_tx_free = cur_tx; 2016 } 2017 2018 if (sc->xl_cdata.xl_tx_head == NULL) { 2019 sc->xl_wdog_timer = 0; 2020 sc->xl_cdata.xl_tx_tail = NULL; 2021 } else { 2022 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2023 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2024 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2025 sc->xl_cdata.xl_tx_head->xl_phys); 2026 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2027 } 2028 } 2029} 2030 2031static void 2032xl_txeof_90xB(struct xl_softc *sc) 2033{ 2034 struct xl_chain *cur_tx = NULL; 2035 if_t ifp = sc->xl_ifp; 2036 int idx; 2037 2038 XL_LOCK_ASSERT(sc); 2039 2040 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2041 BUS_DMASYNC_POSTREAD); 2042 idx = sc->xl_cdata.xl_tx_cons; 2043 while (idx != sc->xl_cdata.xl_tx_prod) { 2044 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2045 2046 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2047 XL_TXSTAT_DL_COMPLETE)) 2048 break; 2049 2050 if (cur_tx->xl_mbuf != NULL) { 2051 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2052 BUS_DMASYNC_POSTWRITE); 2053 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2054 m_freem(cur_tx->xl_mbuf); 2055 cur_tx->xl_mbuf = NULL; 2056 } 2057 2058 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2059 2060 sc->xl_cdata.xl_tx_cnt--; 2061 XL_INC(idx, XL_TX_LIST_CNT); 2062 } 2063 2064 if (sc->xl_cdata.xl_tx_cnt == 0) 2065 sc->xl_wdog_timer = 0; 2066 sc->xl_cdata.xl_tx_cons = idx; 2067 2068 if (cur_tx != NULL) 2069 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2070} 2071 2072/* 2073 * TX 'end of channel' interrupt handler. Actually, we should 2074 * only get a 'TX complete' interrupt if there's a transmit error, 2075 * so this is really TX error handler. 2076 */ 2077static void 2078xl_txeoc(struct xl_softc *sc) 2079{ 2080 u_int8_t txstat; 2081 2082 XL_LOCK_ASSERT(sc); 2083 2084 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2085 if (txstat & XL_TXSTATUS_UNDERRUN || 2086 txstat & XL_TXSTATUS_JABBER || 2087 txstat & XL_TXSTATUS_RECLAIM) { 2088 device_printf(sc->xl_dev, 2089 "transmission error: 0x%02x\n", txstat); 2090 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2091 xl_wait(sc); 2092 if (sc->xl_type == XL_TYPE_905B) { 2093 if (sc->xl_cdata.xl_tx_cnt) { 2094 int i; 2095 struct xl_chain *c; 2096 2097 i = sc->xl_cdata.xl_tx_cons; 2098 c = &sc->xl_cdata.xl_tx_chain[i]; 2099 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2100 c->xl_phys); 2101 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2102 sc->xl_wdog_timer = 5; 2103 } 2104 } else { 2105 if (sc->xl_cdata.xl_tx_head != NULL) { 2106 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2107 sc->xl_cdata.xl_tx_head->xl_phys); 2108 sc->xl_wdog_timer = 5; 2109 } 2110 } 2111 /* 2112 * Remember to set this for the 2113 * first generation 3c90X chips. 2114 */ 2115 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2116 if (txstat & XL_TXSTATUS_UNDERRUN && 2117 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2118 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2119 device_printf(sc->xl_dev, 2120"tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2121 } 2122 CSR_WRITE_2(sc, XL_COMMAND, 2123 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2124 if (sc->xl_type == XL_TYPE_905B) { 2125 CSR_WRITE_2(sc, XL_COMMAND, 2126 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2127 } 2128 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2129 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2130 } else { 2131 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2132 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2133 } 2134 /* 2135 * Write an arbitrary byte to the TX_STATUS register 2136 * to clear this interrupt/error and advance to the next. 2137 */ 2138 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2139 } 2140} 2141 2142static void 2143xl_intr(void *arg) 2144{ 2145 struct xl_softc *sc = arg; 2146 if_t ifp = sc->xl_ifp; 2147 u_int16_t status; 2148 2149 XL_LOCK(sc); 2150 2151#ifdef DEVICE_POLLING 2152 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2153 XL_UNLOCK(sc); 2154 return; 2155 } 2156#endif 2157 2158 for (;;) { 2159 status = CSR_READ_2(sc, XL_STATUS); 2160 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2161 break; 2162 CSR_WRITE_2(sc, XL_COMMAND, 2163 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2164 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2165 break; 2166 2167 if (status & XL_STAT_UP_COMPLETE) { 2168 if (xl_rxeof(sc) == 0) { 2169 while (xl_rx_resync(sc)) 2170 xl_rxeof(sc); 2171 } 2172 } 2173 2174 if (status & XL_STAT_DOWN_COMPLETE) { 2175 if (sc->xl_type == XL_TYPE_905B) 2176 xl_txeof_90xB(sc); 2177 else 2178 xl_txeof(sc); 2179 } 2180 2181 if (status & XL_STAT_TX_COMPLETE) { 2182 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2183 xl_txeoc(sc); 2184 } 2185 2186 if (status & XL_STAT_ADFAIL) { 2187 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2188 xl_init_locked(sc); 2189 break; 2190 } 2191 2192 if (status & XL_STAT_STATSOFLOW) 2193 xl_stats_update(sc); 2194 } 2195 2196 if (!if_sendq_empty(ifp) && 2197 if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2198 if (sc->xl_type == XL_TYPE_905B) 2199 xl_start_90xB_locked(ifp); 2200 else 2201 xl_start_locked(ifp); 2202 } 2203 2204 XL_UNLOCK(sc); 2205} 2206 2207#ifdef DEVICE_POLLING 2208static int 2209xl_poll(if_t ifp, enum poll_cmd cmd, int count) 2210{ 2211 struct xl_softc *sc = if_getsoftc(ifp); 2212 int rx_npkts = 0; 2213 2214 XL_LOCK(sc); 2215 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2216 rx_npkts = xl_poll_locked(ifp, cmd, count); 2217 XL_UNLOCK(sc); 2218 return (rx_npkts); 2219} 2220 2221static int 2222xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2223{ 2224 struct xl_softc *sc = if_getsoftc(ifp); 2225 int rx_npkts; 2226 2227 XL_LOCK_ASSERT(sc); 2228 2229 sc->rxcycles = count; 2230 rx_npkts = xl_rxeof(sc); 2231 if (sc->xl_type == XL_TYPE_905B) 2232 xl_txeof_90xB(sc); 2233 else 2234 xl_txeof(sc); 2235 2236 if (!if_sendq_empty(ifp)) { 2237 if (sc->xl_type == XL_TYPE_905B) 2238 xl_start_90xB_locked(ifp); 2239 else 2240 xl_start_locked(ifp); 2241 } 2242 2243 if (cmd == POLL_AND_CHECK_STATUS) { 2244 u_int16_t status; 2245 2246 status = CSR_READ_2(sc, XL_STATUS); 2247 if (status & XL_INTRS && status != 0xFFFF) { 2248 CSR_WRITE_2(sc, XL_COMMAND, 2249 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2250 2251 if (status & XL_STAT_TX_COMPLETE) { 2252 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2253 xl_txeoc(sc); 2254 } 2255 2256 if (status & XL_STAT_ADFAIL) { 2257 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2258 xl_init_locked(sc); 2259 } 2260 2261 if (status & XL_STAT_STATSOFLOW) 2262 xl_stats_update(sc); 2263 } 2264 } 2265 return (rx_npkts); 2266} 2267#endif /* DEVICE_POLLING */ 2268 2269static void 2270xl_tick(void *xsc) 2271{ 2272 struct xl_softc *sc = xsc; 2273 struct mii_data *mii; 2274 2275 XL_LOCK_ASSERT(sc); 2276 2277 if (sc->xl_miibus != NULL) { 2278 mii = device_get_softc(sc->xl_miibus); 2279 mii_tick(mii); 2280 } 2281 2282 xl_stats_update(sc); 2283 if (xl_watchdog(sc) == EJUSTRETURN) 2284 return; 2285 2286 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2287} 2288 2289static void 2290xl_stats_update(struct xl_softc *sc) 2291{ 2292 if_t ifp = sc->xl_ifp; 2293 struct xl_stats xl_stats; 2294 u_int8_t *p; 2295 int i; 2296 2297 XL_LOCK_ASSERT(sc); 2298 2299 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2300 2301 p = (u_int8_t *)&xl_stats; 2302 2303 /* Read all the stats registers. */ 2304 XL_SEL_WIN(6); 2305 2306 for (i = 0; i < 16; i++) 2307 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2308 2309 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2310 2311 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2312 xl_stats.xl_tx_multi_collision + 2313 xl_stats.xl_tx_single_collision + 2314 xl_stats.xl_tx_late_collision); 2315 2316 /* 2317 * Boomerang and cyclone chips have an extra stats counter 2318 * in window 4 (BadSSD). We have to read this too in order 2319 * to clear out all the stats registers and avoid a statsoflow 2320 * interrupt. 2321 */ 2322 XL_SEL_WIN(4); 2323 CSR_READ_1(sc, XL_W4_BADSSD); 2324 XL_SEL_WIN(7); 2325} 2326 2327/* 2328 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2329 * pointers to the fragment pointers. 2330 */ 2331static int 2332xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2333{ 2334 struct mbuf *m_new; 2335 if_t ifp = sc->xl_ifp; 2336 int error, i, nseg, total_len; 2337 u_int32_t status; 2338 2339 XL_LOCK_ASSERT(sc); 2340 2341 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2342 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2343 2344 if (error && error != EFBIG) { 2345 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2346 return (error); 2347 } 2348 2349 /* 2350 * Handle special case: we used up all 63 fragments, 2351 * but we have more mbufs left in the chain. Copy the 2352 * data into an mbuf cluster. Note that we don't 2353 * bother clearing the values in the other fragment 2354 * pointers/counters; it wouldn't gain us anything, 2355 * and would waste cycles. 2356 */ 2357 if (error) { 2358 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2359 if (m_new == NULL) { 2360 m_freem(*m_head); 2361 *m_head = NULL; 2362 return (ENOBUFS); 2363 } 2364 *m_head = m_new; 2365 2366 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2367 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2368 if (error) { 2369 m_freem(*m_head); 2370 *m_head = NULL; 2371 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2372 return (error); 2373 } 2374 } 2375 2376 KASSERT(nseg <= XL_MAXFRAGS, 2377 ("%s: too many DMA segments (%d)", __func__, nseg)); 2378 if (nseg == 0) { 2379 m_freem(*m_head); 2380 *m_head = NULL; 2381 return (EIO); 2382 } 2383 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2384 2385 total_len = 0; 2386 for (i = 0; i < nseg; i++) { 2387 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2388 ("segment size too large")); 2389 c->xl_ptr->xl_frag[i].xl_addr = 2390 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2391 c->xl_ptr->xl_frag[i].xl_len = 2392 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2393 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2394 } 2395 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2396 2397 if (sc->xl_type == XL_TYPE_905B) { 2398 status = XL_TXSTAT_RND_DEFEAT; 2399 2400#ifndef XL905B_TXCSUM_BROKEN 2401 if ((*m_head)->m_pkthdr.csum_flags) { 2402 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2403 status |= XL_TXSTAT_IPCKSUM; 2404 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2405 status |= XL_TXSTAT_TCPCKSUM; 2406 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2407 status |= XL_TXSTAT_UDPCKSUM; 2408 } 2409#endif 2410 } else 2411 status = total_len; 2412 c->xl_ptr->xl_status = htole32(status); 2413 c->xl_ptr->xl_next = 0; 2414 2415 c->xl_mbuf = *m_head; 2416 return (0); 2417} 2418 2419/* 2420 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2421 * to the mbuf data regions directly in the transmit lists. We also save a 2422 * copy of the pointers since the transmit list fragment pointers are 2423 * physical addresses. 2424 */ 2425 2426static void 2427xl_start(if_t ifp) 2428{ 2429 struct xl_softc *sc = if_getsoftc(ifp); 2430 2431 XL_LOCK(sc); 2432 2433 if (sc->xl_type == XL_TYPE_905B) 2434 xl_start_90xB_locked(ifp); 2435 else 2436 xl_start_locked(ifp); 2437 2438 XL_UNLOCK(sc); 2439} 2440 2441static void 2442xl_start_locked(if_t ifp) 2443{ 2444 struct xl_softc *sc = if_getsoftc(ifp); 2445 struct mbuf *m_head; 2446 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2447 struct xl_chain *prev_tx; 2448 int error; 2449 2450 XL_LOCK_ASSERT(sc); 2451 2452 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2453 IFF_DRV_RUNNING) 2454 return; 2455 /* 2456 * Check for an available queue slot. If there are none, 2457 * punt. 2458 */ 2459 if (sc->xl_cdata.xl_tx_free == NULL) { 2460 xl_txeoc(sc); 2461 xl_txeof(sc); 2462 if (sc->xl_cdata.xl_tx_free == NULL) { 2463 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2464 return; 2465 } 2466 } 2467 2468 start_tx = sc->xl_cdata.xl_tx_free; 2469 2470 for (; !if_sendq_empty(ifp) && 2471 sc->xl_cdata.xl_tx_free != NULL;) { 2472 m_head = if_dequeue(ifp); 2473 if (m_head == NULL) 2474 break; 2475 2476 /* Pick a descriptor off the free list. */ 2477 prev_tx = cur_tx; 2478 cur_tx = sc->xl_cdata.xl_tx_free; 2479 2480 /* Pack the data into the descriptor. */ 2481 error = xl_encap(sc, cur_tx, &m_head); 2482 if (error) { 2483 cur_tx = prev_tx; 2484 if (m_head == NULL) 2485 break; 2486 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2487 if_sendq_prepend(ifp, m_head); 2488 break; 2489 } 2490 2491 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2492 cur_tx->xl_next = NULL; 2493 2494 /* Chain it together. */ 2495 if (prev != NULL) { 2496 prev->xl_next = cur_tx; 2497 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2498 } 2499 prev = cur_tx; 2500 2501 /* 2502 * If there's a BPF listener, bounce a copy of this frame 2503 * to him. 2504 */ 2505 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2506 } 2507 2508 /* 2509 * If there are no packets queued, bail. 2510 */ 2511 if (cur_tx == NULL) 2512 return; 2513 2514 /* 2515 * Place the request for the upload interrupt 2516 * in the last descriptor in the chain. This way, if 2517 * we're chaining several packets at once, we'll only 2518 * get an interrupt once for the whole chain rather than 2519 * once for each packet. 2520 */ 2521 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2522 2523 /* 2524 * Queue the packets. If the TX channel is clear, update 2525 * the downlist pointer register. 2526 */ 2527 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2528 xl_wait(sc); 2529 2530 if (sc->xl_cdata.xl_tx_head != NULL) { 2531 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2532 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2533 htole32(start_tx->xl_phys); 2534 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2535 htole32(~XL_TXSTAT_DL_INTR); 2536 sc->xl_cdata.xl_tx_tail = cur_tx; 2537 } else { 2538 sc->xl_cdata.xl_tx_head = start_tx; 2539 sc->xl_cdata.xl_tx_tail = cur_tx; 2540 } 2541 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2542 BUS_DMASYNC_PREWRITE); 2543 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2544 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2545 2546 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2547 2548 XL_SEL_WIN(7); 2549 2550 /* 2551 * Set a timeout in case the chip goes out to lunch. 2552 */ 2553 sc->xl_wdog_timer = 5; 2554 2555 /* 2556 * XXX Under certain conditions, usually on slower machines 2557 * where interrupts may be dropped, it's possible for the 2558 * adapter to chew up all the buffers in the receive ring 2559 * and stall, without us being able to do anything about it. 2560 * To guard against this, we need to make a pass over the 2561 * RX queue to make sure there aren't any packets pending. 2562 * Doing it here means we can flush the receive ring at the 2563 * same time the chip is DMAing the transmit descriptors we 2564 * just gave it. 2565 * 2566 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2567 * nature of their chips in all their marketing literature; 2568 * we may as well take advantage of it. :) 2569 */ 2570 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2571} 2572 2573static void 2574xl_start_90xB_locked(if_t ifp) 2575{ 2576 struct xl_softc *sc = if_getsoftc(ifp); 2577 struct mbuf *m_head; 2578 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2579 struct xl_chain *prev_tx; 2580 int error, idx; 2581 2582 XL_LOCK_ASSERT(sc); 2583 2584 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2585 IFF_DRV_RUNNING) 2586 return; 2587 2588 idx = sc->xl_cdata.xl_tx_prod; 2589 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2590 2591 for (; !if_sendq_empty(ifp) && 2592 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2593 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2594 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2595 break; 2596 } 2597 2598 m_head = if_dequeue(ifp); 2599 if (m_head == NULL) 2600 break; 2601 2602 prev_tx = cur_tx; 2603 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2604 2605 /* Pack the data into the descriptor. */ 2606 error = xl_encap(sc, cur_tx, &m_head); 2607 if (error) { 2608 cur_tx = prev_tx; 2609 if (m_head == NULL) 2610 break; 2611 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2612 if_sendq_prepend(ifp, m_head); 2613 break; 2614 } 2615 2616 /* Chain it together. */ 2617 if (prev != NULL) 2618 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2619 prev = cur_tx; 2620 2621 /* 2622 * If there's a BPF listener, bounce a copy of this frame 2623 * to him. 2624 */ 2625 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2626 2627 XL_INC(idx, XL_TX_LIST_CNT); 2628 sc->xl_cdata.xl_tx_cnt++; 2629 } 2630 2631 /* 2632 * If there are no packets queued, bail. 2633 */ 2634 if (cur_tx == NULL) 2635 return; 2636 2637 /* 2638 * Place the request for the upload interrupt 2639 * in the last descriptor in the chain. This way, if 2640 * we're chaining several packets at once, we'll only 2641 * get an interrupt once for the whole chain rather than 2642 * once for each packet. 2643 */ 2644 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2645 2646 /* Start transmission */ 2647 sc->xl_cdata.xl_tx_prod = idx; 2648 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2649 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2650 BUS_DMASYNC_PREWRITE); 2651 2652 /* 2653 * Set a timeout in case the chip goes out to lunch. 2654 */ 2655 sc->xl_wdog_timer = 5; 2656} 2657 2658static void 2659xl_init(void *xsc) 2660{ 2661 struct xl_softc *sc = xsc; 2662 2663 XL_LOCK(sc); 2664 xl_init_locked(sc); 2665 XL_UNLOCK(sc); 2666} 2667 2668static void 2669xl_init_locked(struct xl_softc *sc) 2670{ 2671 if_t ifp = sc->xl_ifp; 2672 int error, i; 2673 struct mii_data *mii = NULL; 2674 2675 XL_LOCK_ASSERT(sc); 2676 2677 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2678 return; 2679 /* 2680 * Cancel pending I/O and free all RX/TX buffers. 2681 */ 2682 xl_stop(sc); 2683 2684 /* Reset the chip to a known state. */ 2685 xl_reset(sc); 2686 2687 if (sc->xl_miibus == NULL) { 2688 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2689 xl_wait(sc); 2690 } 2691 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2692 xl_wait(sc); 2693 DELAY(10000); 2694 2695 if (sc->xl_miibus != NULL) 2696 mii = device_get_softc(sc->xl_miibus); 2697 2698 /* 2699 * Clear WOL status and disable all WOL feature as WOL 2700 * would interfere Rx operation under normal environments. 2701 */ 2702 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2703 XL_SEL_WIN(7); 2704 CSR_READ_2(sc, XL_W7_BM_PME); 2705 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2706 } 2707 /* Init our MAC address */ 2708 XL_SEL_WIN(2); 2709 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2710 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2711 if_getlladdr(sc->xl_ifp)[i]); 2712 } 2713 2714 /* Clear the station mask. */ 2715 for (i = 0; i < 3; i++) 2716 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2717#ifdef notdef 2718 /* Reset TX and RX. */ 2719 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2720 xl_wait(sc); 2721 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2722 xl_wait(sc); 2723#endif 2724 /* Init circular RX list. */ 2725 error = xl_list_rx_init(sc); 2726 if (error) { 2727 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2728 error); 2729 xl_stop(sc); 2730 return; 2731 } 2732 2733 /* Init TX descriptors. */ 2734 if (sc->xl_type == XL_TYPE_905B) 2735 error = xl_list_tx_init_90xB(sc); 2736 else 2737 error = xl_list_tx_init(sc); 2738 if (error) { 2739 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2740 error); 2741 xl_stop(sc); 2742 return; 2743 } 2744 2745 /* 2746 * Set the TX freethresh value. 2747 * Note that this has no effect on 3c905B "cyclone" 2748 * cards but is required for 3c900/3c905 "boomerang" 2749 * cards in order to enable the download engine. 2750 */ 2751 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2752 2753 /* Set the TX start threshold for best performance. */ 2754 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2755 2756 /* 2757 * If this is a 3c905B, also set the tx reclaim threshold. 2758 * This helps cut down on the number of tx reclaim errors 2759 * that could happen on a busy network. The chip multiplies 2760 * the register value by 16 to obtain the actual threshold 2761 * in bytes, so we divide by 16 when setting the value here. 2762 * The existing threshold value can be examined by reading 2763 * the register at offset 9 in window 5. 2764 */ 2765 if (sc->xl_type == XL_TYPE_905B) { 2766 CSR_WRITE_2(sc, XL_COMMAND, 2767 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2768 } 2769 2770 /* Set RX filter bits. */ 2771 xl_rxfilter(sc); 2772 2773 /* 2774 * Load the address of the RX list. We have to 2775 * stall the upload engine before we can manipulate 2776 * the uplist pointer register, then unstall it when 2777 * we're finished. We also have to wait for the 2778 * stall command to complete before proceeding. 2779 * Note that we have to do this after any RX resets 2780 * have completed since the uplist register is cleared 2781 * by a reset. 2782 */ 2783 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2784 xl_wait(sc); 2785 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2787 xl_wait(sc); 2788 2789 if (sc->xl_type == XL_TYPE_905B) { 2790 /* Set polling interval */ 2791 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2792 /* Load the address of the TX list */ 2793 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2794 xl_wait(sc); 2795 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2796 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2798 xl_wait(sc); 2799 } 2800 2801 /* 2802 * If the coax transceiver is on, make sure to enable 2803 * the DC-DC converter. 2804 */ 2805 XL_SEL_WIN(3); 2806 if (sc->xl_xcvr == XL_XCVR_COAX) 2807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2808 else 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2810 2811 /* 2812 * increase packet size to allow reception of 802.1q or ISL packets. 2813 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2814 * control register. For 3c90xB/C chips, use the RX packet size 2815 * register. 2816 */ 2817 2818 if (sc->xl_type == XL_TYPE_905B) 2819 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2820 else { 2821 u_int8_t macctl; 2822 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2823 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2824 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2825 } 2826 2827 /* Clear out the stats counters. */ 2828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2829 xl_stats_update(sc); 2830 XL_SEL_WIN(4); 2831 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2833 2834 /* 2835 * Enable interrupts. 2836 */ 2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2839#ifdef DEVICE_POLLING 2840 /* Disable interrupts if we are polling. */ 2841 if (if_getcapenable(ifp) & IFCAP_POLLING) 2842 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2843 else 2844#endif 2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2846 if (sc->xl_flags & XL_FLAG_FUNCREG) 2847 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2848 2849 /* Set the RX early threshold */ 2850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2851 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2852 2853 /* Enable receiver and transmitter. */ 2854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2855 xl_wait(sc); 2856 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2857 xl_wait(sc); 2858 2859 /* XXX Downcall to miibus. */ 2860 if (mii != NULL) 2861 mii_mediachg(mii); 2862 2863 /* Select window 7 for normal operations. */ 2864 XL_SEL_WIN(7); 2865 2866 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2867 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2868 2869 sc->xl_wdog_timer = 0; 2870 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2871} 2872 2873/* 2874 * Set media options. 2875 */ 2876static int 2877xl_ifmedia_upd(if_t ifp) 2878{ 2879 struct xl_softc *sc = if_getsoftc(ifp); 2880 struct ifmedia *ifm = NULL; 2881 struct mii_data *mii = NULL; 2882 2883 XL_LOCK(sc); 2884 2885 if (sc->xl_miibus != NULL) 2886 mii = device_get_softc(sc->xl_miibus); 2887 if (mii == NULL) 2888 ifm = &sc->ifmedia; 2889 else 2890 ifm = &mii->mii_media; 2891 2892 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2893 case IFM_100_FX: 2894 case IFM_10_FL: 2895 case IFM_10_2: 2896 case IFM_10_5: 2897 xl_setmode(sc, ifm->ifm_media); 2898 XL_UNLOCK(sc); 2899 return (0); 2900 } 2901 2902 if (sc->xl_media & XL_MEDIAOPT_MII || 2903 sc->xl_media & XL_MEDIAOPT_BTX || 2904 sc->xl_media & XL_MEDIAOPT_BT4) { 2905 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2906 xl_init_locked(sc); 2907 } else { 2908 xl_setmode(sc, ifm->ifm_media); 2909 } 2910 2911 XL_UNLOCK(sc); 2912 2913 return (0); 2914} 2915 2916/* 2917 * Report current media status. 2918 */ 2919static void 2920xl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2921{ 2922 struct xl_softc *sc = if_getsoftc(ifp); 2923 u_int32_t icfg; 2924 u_int16_t status = 0; 2925 struct mii_data *mii = NULL; 2926 2927 XL_LOCK(sc); 2928 2929 if (sc->xl_miibus != NULL) 2930 mii = device_get_softc(sc->xl_miibus); 2931 2932 XL_SEL_WIN(4); 2933 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2934 2935 XL_SEL_WIN(3); 2936 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2937 icfg >>= XL_ICFG_CONNECTOR_BITS; 2938 2939 ifmr->ifm_active = IFM_ETHER; 2940 ifmr->ifm_status = IFM_AVALID; 2941 2942 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2943 ifmr->ifm_status |= IFM_ACTIVE; 2944 2945 switch (icfg) { 2946 case XL_XCVR_10BT: 2947 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2948 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2949 ifmr->ifm_active |= IFM_FDX; 2950 else 2951 ifmr->ifm_active |= IFM_HDX; 2952 break; 2953 case XL_XCVR_AUI: 2954 if (sc->xl_type == XL_TYPE_905B && 2955 sc->xl_media == XL_MEDIAOPT_10FL) { 2956 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2957 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2958 ifmr->ifm_active |= IFM_FDX; 2959 else 2960 ifmr->ifm_active |= IFM_HDX; 2961 } else 2962 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2963 break; 2964 case XL_XCVR_COAX: 2965 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2966 break; 2967 /* 2968 * XXX MII and BTX/AUTO should be separate cases. 2969 */ 2970 2971 case XL_XCVR_100BTX: 2972 case XL_XCVR_AUTO: 2973 case XL_XCVR_MII: 2974 if (mii != NULL) { 2975 mii_pollstat(mii); 2976 ifmr->ifm_active = mii->mii_media_active; 2977 ifmr->ifm_status = mii->mii_media_status; 2978 } 2979 break; 2980 case XL_XCVR_100BFX: 2981 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2982 break; 2983 default: 2984 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 2985 break; 2986 } 2987 2988 XL_UNLOCK(sc); 2989} 2990 2991static int 2992xl_ioctl(if_t ifp, u_long command, caddr_t data) 2993{ 2994 struct xl_softc *sc = if_getsoftc(ifp); 2995 struct ifreq *ifr = (struct ifreq *) data; 2996 int error = 0, mask; 2997 struct mii_data *mii = NULL; 2998 2999 switch (command) { 3000 case SIOCSIFFLAGS: 3001 XL_LOCK(sc); 3002 if (if_getflags(ifp) & IFF_UP) { 3003 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 3004 (if_getflags(ifp) ^ sc->xl_if_flags) & 3005 (IFF_PROMISC | IFF_ALLMULTI)) 3006 xl_rxfilter(sc); 3007 else 3008 xl_init_locked(sc); 3009 } else { 3010 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3011 xl_stop(sc); 3012 } 3013 sc->xl_if_flags = if_getflags(ifp); 3014 XL_UNLOCK(sc); 3015 break; 3016 case SIOCADDMULTI: 3017 case SIOCDELMULTI: 3018 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3019 XL_LOCK(sc); 3020 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3021 xl_rxfilter(sc); 3022 XL_UNLOCK(sc); 3023 break; 3024 case SIOCGIFMEDIA: 3025 case SIOCSIFMEDIA: 3026 if (sc->xl_miibus != NULL) 3027 mii = device_get_softc(sc->xl_miibus); 3028 if (mii == NULL) 3029 error = ifmedia_ioctl(ifp, ifr, 3030 &sc->ifmedia, command); 3031 else 3032 error = ifmedia_ioctl(ifp, ifr, 3033 &mii->mii_media, command); 3034 break; 3035 case SIOCSIFCAP: 3036 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3037#ifdef DEVICE_POLLING 3038 if ((mask & IFCAP_POLLING) != 0 && 3039 (if_getcapabilities(ifp) & IFCAP_POLLING) != 0) { 3040 if_togglecapenable(ifp, IFCAP_POLLING); 3041 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) { 3042 error = ether_poll_register(xl_poll, ifp); 3043 if (error) 3044 break; 3045 XL_LOCK(sc); 3046 /* Disable interrupts */ 3047 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3048 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3049 XL_UNLOCK(sc); 3050 } else { 3051 error = ether_poll_deregister(ifp); 3052 /* Enable interrupts. */ 3053 XL_LOCK(sc); 3054 CSR_WRITE_2(sc, XL_COMMAND, 3055 XL_CMD_INTR_ACK | 0xFF); 3056 CSR_WRITE_2(sc, XL_COMMAND, 3057 XL_CMD_INTR_ENB | XL_INTRS); 3058 if (sc->xl_flags & XL_FLAG_FUNCREG) 3059 bus_space_write_4(sc->xl_ftag, 3060 sc->xl_fhandle, 4, 0x8000); 3061 XL_UNLOCK(sc); 3062 } 3063 } 3064#endif /* DEVICE_POLLING */ 3065 XL_LOCK(sc); 3066 if ((mask & IFCAP_TXCSUM) != 0 && 3067 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3068 if_togglecapenable(ifp, IFCAP_TXCSUM); 3069 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3070 if_sethwassistbits(ifp, XL905B_CSUM_FEATURES, 0); 3071 else 3072 if_sethwassistbits(ifp, 0, XL905B_CSUM_FEATURES); 3073 } 3074 if ((mask & IFCAP_RXCSUM) != 0 && 3075 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 3076 if_togglecapenable(ifp, IFCAP_RXCSUM); 3077 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3078 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3079 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3080 XL_UNLOCK(sc); 3081 break; 3082 default: 3083 error = ether_ioctl(ifp, command, data); 3084 break; 3085 } 3086 3087 return (error); 3088} 3089 3090static int 3091xl_watchdog(struct xl_softc *sc) 3092{ 3093 if_t ifp = sc->xl_ifp; 3094 u_int16_t status = 0; 3095 int misintr; 3096 3097 XL_LOCK_ASSERT(sc); 3098 3099 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3100 return (0); 3101 3102 xl_rxeof(sc); 3103 xl_txeoc(sc); 3104 misintr = 0; 3105 if (sc->xl_type == XL_TYPE_905B) { 3106 xl_txeof_90xB(sc); 3107 if (sc->xl_cdata.xl_tx_cnt == 0) 3108 misintr++; 3109 } else { 3110 xl_txeof(sc); 3111 if (sc->xl_cdata.xl_tx_head == NULL) 3112 misintr++; 3113 } 3114 if (misintr != 0) { 3115 device_printf(sc->xl_dev, 3116 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3117 return (0); 3118 } 3119 3120 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3121 XL_SEL_WIN(4); 3122 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3123 device_printf(sc->xl_dev, "watchdog timeout\n"); 3124 3125 if (status & XL_MEDIASTAT_CARRIER) 3126 device_printf(sc->xl_dev, 3127 "no carrier - transceiver cable problem?\n"); 3128 3129 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3130 xl_init_locked(sc); 3131 3132 if (!if_sendq_empty(ifp)) { 3133 if (sc->xl_type == XL_TYPE_905B) 3134 xl_start_90xB_locked(ifp); 3135 else 3136 xl_start_locked(ifp); 3137 } 3138 3139 return (EJUSTRETURN); 3140} 3141 3142/* 3143 * Stop the adapter and free any mbufs allocated to the 3144 * RX and TX lists. 3145 */ 3146static void 3147xl_stop(struct xl_softc *sc) 3148{ 3149 int i; 3150 if_t ifp = sc->xl_ifp; 3151 3152 XL_LOCK_ASSERT(sc); 3153 3154 sc->xl_wdog_timer = 0; 3155 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3160 xl_wait(sc); 3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3163 DELAY(800); 3164 3165#ifdef foo 3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3167 xl_wait(sc); 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3169 xl_wait(sc); 3170#endif 3171 3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3175 if (sc->xl_flags & XL_FLAG_FUNCREG) 3176 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3177 3178 /* Stop the stats updater. */ 3179 callout_stop(&sc->xl_tick_callout); 3180 3181 /* 3182 * Free data in the RX lists. 3183 */ 3184 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3185 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3186 bus_dmamap_unload(sc->xl_mtag, 3187 sc->xl_cdata.xl_rx_chain[i].xl_map); 3188 bus_dmamap_destroy(sc->xl_mtag, 3189 sc->xl_cdata.xl_rx_chain[i].xl_map); 3190 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3191 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3192 } 3193 } 3194 if (sc->xl_ldata.xl_rx_list != NULL) 3195 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3196 /* 3197 * Free the TX list buffers. 3198 */ 3199 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3200 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3201 bus_dmamap_unload(sc->xl_mtag, 3202 sc->xl_cdata.xl_tx_chain[i].xl_map); 3203 bus_dmamap_destroy(sc->xl_mtag, 3204 sc->xl_cdata.xl_tx_chain[i].xl_map); 3205 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3206 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3207 } 3208 } 3209 if (sc->xl_ldata.xl_tx_list != NULL) 3210 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3211 3212 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3213} 3214 3215/* 3216 * Stop all chip I/O so that the kernel's probe routines don't 3217 * get confused by errant DMAs when rebooting. 3218 */ 3219static int 3220xl_shutdown(device_t dev) 3221{ 3222 3223 return (xl_suspend(dev)); 3224} 3225 3226static int 3227xl_suspend(device_t dev) 3228{ 3229 struct xl_softc *sc; 3230 3231 sc = device_get_softc(dev); 3232 3233 XL_LOCK(sc); 3234 xl_stop(sc); 3235 xl_setwol(sc); 3236 XL_UNLOCK(sc); 3237 3238 return (0); 3239} 3240 3241static int 3242xl_resume(device_t dev) 3243{ 3244 struct xl_softc *sc; 3245 if_t ifp; 3246 3247 sc = device_get_softc(dev); 3248 ifp = sc->xl_ifp; 3249 3250 XL_LOCK(sc); 3251 3252 if (if_getflags(ifp) & IFF_UP) { 3253 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3254 xl_init_locked(sc); 3255 } 3256 3257 XL_UNLOCK(sc); 3258 3259 return (0); 3260} 3261 3262static void 3263xl_setwol(struct xl_softc *sc) 3264{ 3265 if_t ifp; 3266 u_int16_t cfg, pmstat; 3267 3268 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3269 return; 3270 3271 ifp = sc->xl_ifp; 3272 XL_SEL_WIN(7); 3273 /* Clear any pending PME events. */ 3274 CSR_READ_2(sc, XL_W7_BM_PME); 3275 cfg = 0; 3276 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3277 cfg |= XL_BM_PME_MAGIC; 3278 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3279 /* Enable RX. */ 3280 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3282 /* Request PME. */ 3283 pmstat = pci_read_config(sc->xl_dev, 3284 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3285 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3286 pmstat |= PCIM_PSTAT_PMEENABLE; 3287 else 3288 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3289 pci_write_config(sc->xl_dev, 3290 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3291} 3292