/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 264 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 279 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 358 unsigned Op1, Op2; local 359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 363 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 371 unsigned Op1, Op2; local 372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 376 Inst.addOperand(MCOperand::CreateImm(Op1)); 384 unsigned Op1, Op2; local 397 unsigned Op1, Op2; local 411 unsigned Op1, Op2; local 424 unsigned Op1, Op2; local 437 unsigned Op1, Op2; local 522 unsigned Op1, Op2; local 536 unsigned Op1, Op2; local 550 unsigned Op1, Op2, Op3; local 563 unsigned Op1, Op2, Op3; local 576 unsigned Op1, Op2, Op3; local 589 unsigned Op1, Op2, Op3; local 602 unsigned Op1, Op2, Op3; local 616 unsigned Op1, Op2, Op3; local 631 unsigned Op1, Op2, Op3; local 645 unsigned Op1, Op2, Op3; local 659 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 693 unsigned Op1, Op2, Op3, Op4, Op5; local 713 unsigned Op1, Op2, Op3; local 732 unsigned Op1, Op2, Op3; local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) 161 if (Op1->getOpcode() == OpcodeToExpand) { 163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); 198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); local 201 !Op1 || Op1->getOpcode() != OpcodeToExtract) 206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1); 269 BinaryOperator *Op1 local 592 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 653 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 734 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 859 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 868 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 910 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 946 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 974 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1037 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1043 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1049 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1057 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1065 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1137 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1145 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1153 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1161 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1167 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument 1180 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1188 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1242 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1250 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1258 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1266 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1272 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument 1285 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1293 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1337 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1353 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1362 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1384 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1394 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1420 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1430 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1521 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1529 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1615 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1623 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1675 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument [all...] |
H A D | ConstantFolding.cpp | 557 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression. 562 Constant *Op1, const DataLayout *DL){ 575 ComputeMaskedBits(Op1, KnownZero1, KnownOne1, DL); 581 // All the bits of Op1 that the 'and' could be masking are already zero. 582 return Op1; 599 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) && 1526 if (ConstantFP *Op1 = dyn_cast<ConstantFP>(Operands[0])) { 1531 Op1V = Op1->getValueAPF().convertToFloat(); 1533 Op1V = Op1->getValueAPF().convertToDouble(); 1536 APFloat APF = Op1 561 SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, Constant *Op1, const DataLayout *DL) argument [all...] |
/freebsd-9.3-release/sys/contrib/dev/acpica/compiler/ |
H A D | asltree.c | 788 * PARAMETERS: Op1 - First peer 791 * RETURN: Op1 or the non-null node. 799 ACPI_PARSE_OBJECT *Op1, 807 Op1, Op1 ? UtGetOpName(Op1->Asl.ParseOpcode) : NULL, 811 if ((!Op1) && (!Op2)) 814 return Op1; 821 return Op1; 824 if (!Op1) 798 TrLinkPeerNode( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument 935 TrLinkChildNode( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 119 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 121 if (Value *V = SimplifyMulInst(Op0, Op1, TD)) 127 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X 160 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { 195 if (isa<Constant>(Op1)) { 207 if (Value *Op1v = dyn_castNegVal(Op1)) 213 Value *Op1C = Op1; 219 BO = dyn_cast<BinaryOperator>(Op1); 251 return BinaryOperator::CreateAnd(Op0, Op1); 258 return BinaryOperator::CreateShl(Op1, 407 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 674 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 767 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 777 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 786 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 808 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 847 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 908 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 989 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1114 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1146 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1178 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1249 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1)) 44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { 48 Op1->getName()); 312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, argument 320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) { 325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this)); 336 if (Op1 [all...] |
H A D | InstCombineCompares.cpp | 2049 /// \brief Check if the order of \p Op0 and \p Op1 as operand in an ICmpInst 2056 /// \return true if Op0 and Op1 should be swapped. 2058 const Value * Op1) { 2063 // Count every uses of both Op0 and Op1 in a subtract. 2083 if (BinOp->getOperand(Op1Idx) != Op1) 2092 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2094 unsigned Op1Cplxity = getComplexity(Op1); 2101 swapMayExposeCSEOpportunities(Op0, Op1))) { 2103 std::swap(Op0, Op1); 2107 if (Value *V = SimplifyICmpInst(I.getPredicate(), Op0, Op1, T 2057 swapMayExposeCSEOpportunities(const Value * Op0, const Value * Op1) argument 2510 Value *Op1 = 0, *Op2 = 0; local 3230 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 3320 Value *Op1 = 0, *Op2 = 0; local [all...] |
H A D | InstCombineAddSub.cpp | 1353 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1355 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(), 1364 if (Value *V = dyn_castNegVal(Op1)) { 1372 return BinaryOperator::CreateXor(Op0, Op1); 1376 return BinaryOperator::CreateNot(Op1); 1381 if (match(Op1, m_Not(m_Value(X)))) 1388 if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) && 1393 if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) && 1400 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 1406 if (match(Op1, m_Ad 1521 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAndOrXor.cpp | 794 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 797 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); 1100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1102 if (Value *V = SimplifyAndInst(Op0, Op1, TD)) 1114 if (ConstantInt *AndRHS = dyn_cast<ConstantInt>(Op1)) { 1221 if (Value *Op1NotVal = dyn_castNotVal(Op1)) 1222 if (Op0->hasOneUse() && Op1->hasOneUse()) { 1232 match(Op1, m_Not(m_And(m_Value(C), m_Value(D)))) && 1237 if (match(Op1, m_Or(m_Value(A), m_Value(B))) && 1245 Value *tmpOp1 = Op1; 1607 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1918 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2250 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2482 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstructionCombining.cpp | 214 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1)); local 247 if (Op1 && Op1->getOpcode() == Opcode) { 249 Value *B = Op1->getOperand(0); 250 Value *C = Op1->getOperand(1); 289 if (Op1 && Op1->getOpcode() == Opcode) { 291 Value *B = Op1->getOperand(0); 292 Value *C = Op1->getOperand(1); 310 if (Op0 && Op1 399 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); local 565 Value *Op0 = SO, *Op1 = ConstOperand; local [all...] |
/freebsd-9.3-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 199 unsigned Op1, bool Op1IsKill); 226 unsigned Op1, bool Op1IsKill, 270 unsigned Op1, bool Op1IsKill); 277 unsigned Op1, bool Op1IsKill, 305 unsigned Op1, bool Op1IsKill, 313 unsigned Op1, bool Op1IsKill,
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H A D | ISDOpcodes.h | 789 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 795 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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H A D | SelectionDAG.h | 572 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 577 Ops.push_back(Op1); 827 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 828 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 830 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 832 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 842 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1); 844 SDValue Op1, SDValue Op2); 846 SDValue Op1, SDValue Op2, SDValue Op3); 858 EVT VT2, SDValue Op1); [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 202 SDValue Op0, Op1; local 206 if (!SelectADDRrr(Op, Op0, Op1)) 207 SelectADDRri(Op, Op0, Op1); 212 OutOps.push_back(Op1);
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/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 168 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1)); 169 if (!Op1) return false; 175 C->getOperand(0), Op1, *PI, C->getParent()); 181 C->getOperand(0), Op1, *PI, C->getParent());
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 586 SDValue Op1 = Op.getOperand(1); local 590 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 622 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 629 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 631 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 661 SDValue Op1 = Op.getOperand(1); local 683 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits()) 689 Op1 [all...] |
H A D | FastISel.cpp | 382 unsigned Op1 = getRegForValue(I->getOperand(1)); local 383 if (Op1 == 0) return false; 387 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 443 unsigned Op1 = getRegForValue(I->getOperand(1)); local 444 if (Op1 == 0) 454 Op1, Op1IsKill); 1126 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1156 unsigned /*Op1*/, bool /*Op1IsKill*/, 1238 unsigned Op1, bool Op1IsKill) { 1245 .addReg(Op1, Op1IsKil 1235 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1256 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1345 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1369 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument [all...] |
/freebsd-9.3-release/contrib/llvm/include/llvm/Analysis/ |
H A D | InstructionSimplify.h | 128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
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/freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1167 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1169 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1176 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1184 moveToTop(Op1, I); 1185 TOS = Op1; 1207 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1214 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1232 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1240 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1265 unsigned Op1 [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 153 ICToken Op1 = OperandStack.pop_back_val(); local 159 Val = Op1.second + Op2.second; 163 Val = Op1.second - Op2.second; 167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 169 Val = Op1.second * Op2.second; 173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 176 Val = Op1.second / Op2.second; 2168 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); local 2170 if (isSrcOp(*Op1) && Op2->isReg()) { 2187 delete Op1; 2198 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); local 2234 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]); local 2241 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); local 2253 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]); local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397 // between the base and index. Try to fold Op1 into AM's displacement. 399 SDValue Op0, uint64_t Op1) { 401 int64_t TestDisp = AM.Disp + Op1; 423 SDValue Op1 = N.getOperand(1); local 426 unsigned Op1Code = Op1->getOpcode(); 429 return expandAdjDynAlloc(AM, IsBase, Op1); 434 return expandDisp(AM, IsBase, Op1, 438 cast<ConstantSDNode>(Op1)->getSExtValue()); 440 if (IsBase && expandIndex(AM, Op0, Op1)) 398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 1098 SDValue Op1 = Node->getOperand(1); local [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 402 SDValue Op1 = N->getOperand(1); local 407 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 414 unsigned Op1Opc = Op1.getOpcode(); 424 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 425 Op1.getOperand(0).getOpcode() != ISD::SRL) { 426 std::swap(Op0, Op1); 432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 433 Op1.getOperand(0).getOpcode() != ISD::SRL) { 434 std::swap(Op0, Op1); 445 isInt32Immediate(Op1 [all...] |
/freebsd-9.3-release/contrib/llvm/lib/DebugInfo/ |
H A D | DWARFDebugFrame.cpp | 110 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK; local 115 addInstruction(Primary, Op1); 118 addInstruction(Primary, Op1, Data.getULEB128(Offset));
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