1251607Sdim//===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim// 10251607Sdim// This file defines an instruction selector for the SystemZ target. 11251607Sdim// 12251607Sdim//===----------------------------------------------------------------------===// 13251607Sdim 14251607Sdim#include "SystemZTargetMachine.h" 15263509Sdim#include "llvm/Analysis/AliasAnalysis.h" 16251607Sdim#include "llvm/CodeGen/SelectionDAGISel.h" 17251607Sdim#include "llvm/Support/Debug.h" 18251607Sdim#include "llvm/Support/raw_ostream.h" 19251607Sdim 20251607Sdimusing namespace llvm; 21251607Sdim 22251607Sdimnamespace { 23251607Sdim// Used to build addressing modes. 24251607Sdimstruct SystemZAddressingMode { 25251607Sdim // The shape of the address. 26251607Sdim enum AddrForm { 27251607Sdim // base+displacement 28251607Sdim FormBD, 29251607Sdim 30251607Sdim // base+displacement+index for load and store operands 31251607Sdim FormBDXNormal, 32251607Sdim 33251607Sdim // base+displacement+index for load address operands 34251607Sdim FormBDXLA, 35251607Sdim 36251607Sdim // base+displacement+index+ADJDYNALLOC 37251607Sdim FormBDXDynAlloc 38251607Sdim }; 39251607Sdim AddrForm Form; 40251607Sdim 41251607Sdim // The type of displacement. The enum names here correspond directly 42251607Sdim // to the definitions in SystemZOperand.td. We could split them into 43251607Sdim // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 44251607Sdim enum DispRange { 45251607Sdim Disp12Only, 46251607Sdim Disp12Pair, 47251607Sdim Disp20Only, 48251607Sdim Disp20Only128, 49251607Sdim Disp20Pair 50251607Sdim }; 51251607Sdim DispRange DR; 52251607Sdim 53251607Sdim // The parts of the address. The address is equivalent to: 54251607Sdim // 55251607Sdim // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 56251607Sdim SDValue Base; 57251607Sdim int64_t Disp; 58251607Sdim SDValue Index; 59251607Sdim bool IncludesDynAlloc; 60251607Sdim 61251607Sdim SystemZAddressingMode(AddrForm form, DispRange dr) 62251607Sdim : Form(form), DR(dr), Base(), Disp(0), Index(), 63251607Sdim IncludesDynAlloc(false) {} 64251607Sdim 65251607Sdim // True if the address can have an index register. 66251607Sdim bool hasIndexField() { return Form != FormBD; } 67251607Sdim 68251607Sdim // True if the address can (and must) include ADJDYNALLOC. 69251607Sdim bool isDynAlloc() { return Form == FormBDXDynAlloc; } 70251607Sdim 71251607Sdim void dump() { 72251607Sdim errs() << "SystemZAddressingMode " << this << '\n'; 73251607Sdim 74251607Sdim errs() << " Base "; 75251607Sdim if (Base.getNode() != 0) 76251607Sdim Base.getNode()->dump(); 77251607Sdim else 78251607Sdim errs() << "null\n"; 79251607Sdim 80251607Sdim if (hasIndexField()) { 81251607Sdim errs() << " Index "; 82251607Sdim if (Index.getNode() != 0) 83251607Sdim Index.getNode()->dump(); 84251607Sdim else 85251607Sdim errs() << "null\n"; 86251607Sdim } 87251607Sdim 88251607Sdim errs() << " Disp " << Disp; 89251607Sdim if (IncludesDynAlloc) 90251607Sdim errs() << " + ADJDYNALLOC"; 91251607Sdim errs() << '\n'; 92251607Sdim } 93251607Sdim}; 94251607Sdim 95263509Sdim// Return a mask with Count low bits set. 96263509Sdimstatic uint64_t allOnes(unsigned int Count) { 97263509Sdim return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1; 98263509Sdim} 99263509Sdim 100263509Sdim// Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation 101263509Sdim// given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and 102263509Sdim// Rotate (I5). The combined operand value is effectively: 103263509Sdim// 104263509Sdim// (or (rotl Input, Rotate), ~Mask) 105263509Sdim// 106263509Sdim// for RNSBG and: 107263509Sdim// 108263509Sdim// (and (rotl Input, Rotate), Mask) 109263509Sdim// 110263509Sdim// otherwise. The output value has BitSize bits, although Input may be 111263509Sdim// narrower (in which case the upper bits are don't care). 112263509Sdimstruct RxSBGOperands { 113263509Sdim RxSBGOperands(unsigned Op, SDValue N) 114263509Sdim : Opcode(Op), BitSize(N.getValueType().getSizeInBits()), 115263509Sdim Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), 116263509Sdim Rotate(0) {} 117263509Sdim 118263509Sdim unsigned Opcode; 119263509Sdim unsigned BitSize; 120263509Sdim uint64_t Mask; 121263509Sdim SDValue Input; 122263509Sdim unsigned Start; 123263509Sdim unsigned End; 124263509Sdim unsigned Rotate; 125263509Sdim}; 126263509Sdim 127251607Sdimclass SystemZDAGToDAGISel : public SelectionDAGISel { 128251607Sdim const SystemZTargetLowering &Lowering; 129251607Sdim const SystemZSubtarget &Subtarget; 130251607Sdim 131251607Sdim // Used by SystemZOperands.td to create integer constants. 132263509Sdim inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { 133251607Sdim return CurDAG->getTargetConstant(Imm, Node->getValueType(0)); 134251607Sdim } 135251607Sdim 136263509Sdim const SystemZTargetMachine &getTargetMachine() const { 137263509Sdim return static_cast<const SystemZTargetMachine &>(TM); 138263509Sdim } 139263509Sdim 140263509Sdim const SystemZInstrInfo *getInstrInfo() const { 141263509Sdim return getTargetMachine().getInstrInfo(); 142263509Sdim } 143263509Sdim 144251607Sdim // Try to fold more of the base or index of AM into AM, where IsBase 145251607Sdim // selects between the base and index. 146263509Sdim bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const; 147251607Sdim 148251607Sdim // Try to describe N in AM, returning true on success. 149263509Sdim bool selectAddress(SDValue N, SystemZAddressingMode &AM) const; 150251607Sdim 151251607Sdim // Extract individual target operands from matched address AM. 152251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 153263509Sdim SDValue &Base, SDValue &Disp) const; 154251607Sdim void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 155263509Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 156251607Sdim 157251607Sdim // Try to match Addr as a FormBD address with displacement type DR. 158251607Sdim // Return true on success, storing the base and displacement in 159251607Sdim // Base and Disp respectively. 160251607Sdim bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 161263509Sdim SDValue &Base, SDValue &Disp) const; 162251607Sdim 163263509Sdim // Try to match Addr as a FormBDX address with displacement type DR. 164263509Sdim // Return true on success and if the result had no index. Store the 165263509Sdim // base and displacement in Base and Disp respectively. 166263509Sdim bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 167263509Sdim SDValue &Base, SDValue &Disp) const; 168263509Sdim 169251607Sdim // Try to match Addr as a FormBDX* address of form Form with 170251607Sdim // displacement type DR. Return true on success, storing the base, 171251607Sdim // displacement and index in Base, Disp and Index respectively. 172251607Sdim bool selectBDXAddr(SystemZAddressingMode::AddrForm Form, 173251607Sdim SystemZAddressingMode::DispRange DR, SDValue Addr, 174263509Sdim SDValue &Base, SDValue &Disp, SDValue &Index) const; 175251607Sdim 176251607Sdim // PC-relative address matching routines used by SystemZOperands.td. 177263509Sdim bool selectPCRelAddress(SDValue Addr, SDValue &Target) const { 178263509Sdim if (SystemZISD::isPCREL(Addr.getOpcode())) { 179251607Sdim Target = Addr.getOperand(0); 180251607Sdim return true; 181251607Sdim } 182251607Sdim return false; 183251607Sdim } 184251607Sdim 185251607Sdim // BD matching routines used by SystemZOperands.td. 186263509Sdim bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 187251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); 188251607Sdim } 189263509Sdim bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 190251607Sdim return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 191251607Sdim } 192263509Sdim bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 193251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp); 194251607Sdim } 195263509Sdim bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 196251607Sdim return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 197251607Sdim } 198251607Sdim 199263509Sdim // MVI matching routines used by SystemZOperands.td. 200263509Sdim bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 201263509Sdim return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 202263509Sdim } 203263509Sdim bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 204263509Sdim return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 205263509Sdim } 206263509Sdim 207251607Sdim // BDX matching routines used by SystemZOperands.td. 208251607Sdim bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 209263509Sdim SDValue &Index) const { 210251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 211251607Sdim SystemZAddressingMode::Disp12Only, 212251607Sdim Addr, Base, Disp, Index); 213251607Sdim } 214251607Sdim bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 215263509Sdim SDValue &Index) const { 216251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 217251607Sdim SystemZAddressingMode::Disp12Pair, 218251607Sdim Addr, Base, Disp, Index); 219251607Sdim } 220251607Sdim bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 221263509Sdim SDValue &Index) const { 222251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc, 223251607Sdim SystemZAddressingMode::Disp12Only, 224251607Sdim Addr, Base, Disp, Index); 225251607Sdim } 226251607Sdim bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, 227263509Sdim SDValue &Index) const { 228251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 229251607Sdim SystemZAddressingMode::Disp20Only, 230251607Sdim Addr, Base, Disp, Index); 231251607Sdim } 232251607Sdim bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, 233263509Sdim SDValue &Index) const { 234251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 235251607Sdim SystemZAddressingMode::Disp20Only128, 236251607Sdim Addr, Base, Disp, Index); 237251607Sdim } 238251607Sdim bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 239263509Sdim SDValue &Index) const { 240251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 241251607Sdim SystemZAddressingMode::Disp20Pair, 242251607Sdim Addr, Base, Disp, Index); 243251607Sdim } 244251607Sdim bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 245263509Sdim SDValue &Index) const { 246251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 247251607Sdim SystemZAddressingMode::Disp12Pair, 248251607Sdim Addr, Base, Disp, Index); 249251607Sdim } 250251607Sdim bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 251263509Sdim SDValue &Index) const { 252251607Sdim return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 253251607Sdim SystemZAddressingMode::Disp20Pair, 254251607Sdim Addr, Base, Disp, Index); 255251607Sdim } 256251607Sdim 257263509Sdim // Check whether (or Op (and X InsertMask)) is effectively an insertion 258263509Sdim // of X into bits InsertMask of some Y != Op. Return true if so and 259263509Sdim // set Op to that Y. 260263509Sdim bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const; 261263509Sdim 262263509Sdim // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used. 263263509Sdim // Return true on success. 264263509Sdim bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const; 265263509Sdim 266263509Sdim // Try to fold some of RxSBG.Input into other fields of RxSBG. 267263509Sdim // Return true on success. 268263509Sdim bool expandRxSBG(RxSBGOperands &RxSBG) const; 269263509Sdim 270263509Sdim // Return an undefined value of type VT. 271263509Sdim SDValue getUNDEF(SDLoc DL, EVT VT) const; 272263509Sdim 273263509Sdim // Convert N to VT, if it isn't already. 274263509Sdim SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const; 275263509Sdim 276263509Sdim // Try to implement AND or shift node N using RISBG with the zero flag set. 277263509Sdim // Return the selected node on success, otherwise return null. 278263509Sdim SDNode *tryRISBGZero(SDNode *N); 279263509Sdim 280263509Sdim // Try to use RISBG or Opcode to implement OR or XOR node N. 281263509Sdim // Return the selected node on success, otherwise return null. 282263509Sdim SDNode *tryRxSBG(SDNode *N, unsigned Opcode); 283263509Sdim 284251607Sdim // If Op0 is null, then Node is a constant that can be loaded using: 285251607Sdim // 286251607Sdim // (Opcode UpperVal LowerVal) 287251607Sdim // 288251607Sdim // If Op0 is nonnull, then Node can be implemented using: 289251607Sdim // 290251607Sdim // (Opcode (Opcode Op0 UpperVal) LowerVal) 291251607Sdim SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 292251607Sdim uint64_t UpperVal, uint64_t LowerVal); 293251607Sdim 294263509Sdim // Return true if Load and Store are loads and stores of the same size 295263509Sdim // and are guaranteed not to overlap. Such operations can be implemented 296263509Sdim // using block (SS-format) instructions. 297263509Sdim // 298263509Sdim // Partial overlap would lead to incorrect code, since the block operations 299263509Sdim // are logically bytewise, even though they have a fast path for the 300263509Sdim // non-overlapping case. We also need to avoid full overlap (i.e. two 301263509Sdim // addresses that might be equal at run time) because although that case 302263509Sdim // would be handled correctly, it might be implemented by millicode. 303263509Sdim bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const; 304263509Sdim 305263509Sdim // N is a (store (load Y), X) pattern. Return true if it can use an MVC 306263509Sdim // from Y to X. 307263509Sdim bool storeLoadCanUseMVC(SDNode *N) const; 308263509Sdim 309263509Sdim // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true 310263509Sdim // if A[1 - I] == X and if N can use a block operation like NC from A[I] 311263509Sdim // to X. 312263509Sdim bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const; 313263509Sdim 314251607Sdimpublic: 315251607Sdim SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 316251607Sdim : SelectionDAGISel(TM, OptLevel), 317251607Sdim Lowering(*TM.getTargetLowering()), 318251607Sdim Subtarget(*TM.getSubtargetImpl()) { } 319251607Sdim 320251607Sdim // Override MachineFunctionPass. 321251607Sdim virtual const char *getPassName() const LLVM_OVERRIDE { 322251607Sdim return "SystemZ DAG->DAG Pattern Instruction Selection"; 323251607Sdim } 324251607Sdim 325251607Sdim // Override SelectionDAGISel. 326251607Sdim virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE; 327251607Sdim virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 328251607Sdim char ConstraintCode, 329251607Sdim std::vector<SDValue> &OutOps) 330251607Sdim LLVM_OVERRIDE; 331251607Sdim 332251607Sdim // Include the pieces autogenerated from the target description. 333251607Sdim #include "SystemZGenDAGISel.inc" 334251607Sdim}; 335251607Sdim} // end anonymous namespace 336251607Sdim 337251607SdimFunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 338251607Sdim CodeGenOpt::Level OptLevel) { 339251607Sdim return new SystemZDAGToDAGISel(TM, OptLevel); 340251607Sdim} 341251607Sdim 342251607Sdim// Return true if Val should be selected as a displacement for an address 343251607Sdim// with range DR. Here we're interested in the range of both the instruction 344251607Sdim// described by DR and of any pairing instruction. 345251607Sdimstatic bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 346251607Sdim switch (DR) { 347251607Sdim case SystemZAddressingMode::Disp12Only: 348251607Sdim return isUInt<12>(Val); 349251607Sdim 350251607Sdim case SystemZAddressingMode::Disp12Pair: 351251607Sdim case SystemZAddressingMode::Disp20Only: 352251607Sdim case SystemZAddressingMode::Disp20Pair: 353251607Sdim return isInt<20>(Val); 354251607Sdim 355251607Sdim case SystemZAddressingMode::Disp20Only128: 356251607Sdim return isInt<20>(Val) && isInt<20>(Val + 8); 357251607Sdim } 358251607Sdim llvm_unreachable("Unhandled displacement range"); 359251607Sdim} 360251607Sdim 361251607Sdim// Change the base or index in AM to Value, where IsBase selects 362251607Sdim// between the base and index. 363251607Sdimstatic void changeComponent(SystemZAddressingMode &AM, bool IsBase, 364251607Sdim SDValue Value) { 365251607Sdim if (IsBase) 366251607Sdim AM.Base = Value; 367251607Sdim else 368251607Sdim AM.Index = Value; 369251607Sdim} 370251607Sdim 371251607Sdim// The base or index of AM is equivalent to Value + ADJDYNALLOC, 372251607Sdim// where IsBase selects between the base and index. Try to fold the 373251607Sdim// ADJDYNALLOC into AM. 374251607Sdimstatic bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, 375251607Sdim SDValue Value) { 376251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { 377251607Sdim changeComponent(AM, IsBase, Value); 378251607Sdim AM.IncludesDynAlloc = true; 379251607Sdim return true; 380251607Sdim } 381251607Sdim return false; 382251607Sdim} 383251607Sdim 384251607Sdim// The base of AM is equivalent to Base + Index. Try to use Index as 385251607Sdim// the index register. 386251607Sdimstatic bool expandIndex(SystemZAddressingMode &AM, SDValue Base, 387251607Sdim SDValue Index) { 388251607Sdim if (AM.hasIndexField() && !AM.Index.getNode()) { 389251607Sdim AM.Base = Base; 390251607Sdim AM.Index = Index; 391251607Sdim return true; 392251607Sdim } 393251607Sdim return false; 394251607Sdim} 395251607Sdim 396251607Sdim// The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397251607Sdim// between the base and index. Try to fold Op1 into AM's displacement. 398251607Sdimstatic bool expandDisp(SystemZAddressingMode &AM, bool IsBase, 399263509Sdim SDValue Op0, uint64_t Op1) { 400251607Sdim // First try adjusting the displacement. 401263509Sdim int64_t TestDisp = AM.Disp + Op1; 402251607Sdim if (selectDisp(AM.DR, TestDisp)) { 403251607Sdim changeComponent(AM, IsBase, Op0); 404251607Sdim AM.Disp = TestDisp; 405251607Sdim return true; 406251607Sdim } 407251607Sdim 408251607Sdim // We could consider forcing the displacement into a register and 409251607Sdim // using it as an index, but it would need to be carefully tuned. 410251607Sdim return false; 411251607Sdim} 412251607Sdim 413251607Sdimbool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM, 414263509Sdim bool IsBase) const { 415251607Sdim SDValue N = IsBase ? AM.Base : AM.Index; 416251607Sdim unsigned Opcode = N.getOpcode(); 417251607Sdim if (Opcode == ISD::TRUNCATE) { 418251607Sdim N = N.getOperand(0); 419251607Sdim Opcode = N.getOpcode(); 420251607Sdim } 421251607Sdim if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 422251607Sdim SDValue Op0 = N.getOperand(0); 423251607Sdim SDValue Op1 = N.getOperand(1); 424251607Sdim 425251607Sdim unsigned Op0Code = Op0->getOpcode(); 426251607Sdim unsigned Op1Code = Op1->getOpcode(); 427251607Sdim 428251607Sdim if (Op0Code == SystemZISD::ADJDYNALLOC) 429251607Sdim return expandAdjDynAlloc(AM, IsBase, Op1); 430251607Sdim if (Op1Code == SystemZISD::ADJDYNALLOC) 431251607Sdim return expandAdjDynAlloc(AM, IsBase, Op0); 432251607Sdim 433251607Sdim if (Op0Code == ISD::Constant) 434263509Sdim return expandDisp(AM, IsBase, Op1, 435263509Sdim cast<ConstantSDNode>(Op0)->getSExtValue()); 436251607Sdim if (Op1Code == ISD::Constant) 437263509Sdim return expandDisp(AM, IsBase, Op0, 438263509Sdim cast<ConstantSDNode>(Op1)->getSExtValue()); 439251607Sdim 440251607Sdim if (IsBase && expandIndex(AM, Op0, Op1)) 441251607Sdim return true; 442251607Sdim } 443263509Sdim if (Opcode == SystemZISD::PCREL_OFFSET) { 444263509Sdim SDValue Full = N.getOperand(0); 445263509Sdim SDValue Base = N.getOperand(1); 446263509Sdim SDValue Anchor = Base.getOperand(0); 447263509Sdim uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() - 448263509Sdim cast<GlobalAddressSDNode>(Anchor)->getOffset()); 449263509Sdim return expandDisp(AM, IsBase, Base, Offset); 450263509Sdim } 451251607Sdim return false; 452251607Sdim} 453251607Sdim 454251607Sdim// Return true if an instruction with displacement range DR should be 455251607Sdim// used for displacement value Val. selectDisp(DR, Val) must already hold. 456251607Sdimstatic bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 457251607Sdim assert(selectDisp(DR, Val) && "Invalid displacement"); 458251607Sdim switch (DR) { 459251607Sdim case SystemZAddressingMode::Disp12Only: 460251607Sdim case SystemZAddressingMode::Disp20Only: 461251607Sdim case SystemZAddressingMode::Disp20Only128: 462251607Sdim return true; 463251607Sdim 464251607Sdim case SystemZAddressingMode::Disp12Pair: 465251607Sdim // Use the other instruction if the displacement is too large. 466251607Sdim return isUInt<12>(Val); 467251607Sdim 468251607Sdim case SystemZAddressingMode::Disp20Pair: 469251607Sdim // Use the other instruction if the displacement is small enough. 470251607Sdim return !isUInt<12>(Val); 471251607Sdim } 472251607Sdim llvm_unreachable("Unhandled displacement range"); 473251607Sdim} 474251607Sdim 475251607Sdim// Return true if Base + Disp + Index should be performed by LA(Y). 476251607Sdimstatic bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) { 477251607Sdim // Don't use LA(Y) for constants. 478251607Sdim if (!Base) 479251607Sdim return false; 480251607Sdim 481251607Sdim // Always use LA(Y) for frame addresses, since we know that the destination 482251607Sdim // register is almost always (perhaps always) going to be different from 483251607Sdim // the frame register. 484251607Sdim if (Base->getOpcode() == ISD::FrameIndex) 485251607Sdim return true; 486251607Sdim 487251607Sdim if (Disp) { 488251607Sdim // Always use LA(Y) if there is a base, displacement and index. 489251607Sdim if (Index) 490251607Sdim return true; 491251607Sdim 492251607Sdim // Always use LA if the displacement is small enough. It should always 493251607Sdim // be no worse than AGHI (and better if it avoids a move). 494251607Sdim if (isUInt<12>(Disp)) 495251607Sdim return true; 496251607Sdim 497251607Sdim // For similar reasons, always use LAY if the constant is too big for AGHI. 498251607Sdim // LAY should be no worse than AGFI. 499251607Sdim if (!isInt<16>(Disp)) 500251607Sdim return true; 501251607Sdim } else { 502251607Sdim // Don't use LA for plain registers. 503251607Sdim if (!Index) 504251607Sdim return false; 505251607Sdim 506251607Sdim // Don't use LA for plain addition if the index operand is only used 507251607Sdim // once. It should be a natural two-operand addition in that case. 508251607Sdim if (Index->hasOneUse()) 509251607Sdim return false; 510251607Sdim 511251607Sdim // Prefer addition if the second operation is sign-extended, in the 512251607Sdim // hope of using AGF. 513251607Sdim unsigned IndexOpcode = Index->getOpcode(); 514251607Sdim if (IndexOpcode == ISD::SIGN_EXTEND || 515251607Sdim IndexOpcode == ISD::SIGN_EXTEND_INREG) 516251607Sdim return false; 517251607Sdim } 518251607Sdim 519251607Sdim // Don't use LA for two-operand addition if either operand is only 520251607Sdim // used once. The addition instructions are better in that case. 521251607Sdim if (Base->hasOneUse()) 522251607Sdim return false; 523251607Sdim 524251607Sdim return true; 525251607Sdim} 526251607Sdim 527251607Sdim// Return true if Addr is suitable for AM, updating AM if so. 528251607Sdimbool SystemZDAGToDAGISel::selectAddress(SDValue Addr, 529263509Sdim SystemZAddressingMode &AM) const { 530251607Sdim // Start out assuming that the address will need to be loaded separately, 531251607Sdim // then try to extend it as much as we can. 532251607Sdim AM.Base = Addr; 533251607Sdim 534251607Sdim // First try treating the address as a constant. 535251607Sdim if (Addr.getOpcode() == ISD::Constant && 536263509Sdim expandDisp(AM, true, SDValue(), 537263509Sdim cast<ConstantSDNode>(Addr)->getSExtValue())) 538251607Sdim ; 539251607Sdim else 540251607Sdim // Otherwise try expanding each component. 541251607Sdim while (expandAddress(AM, true) || 542251607Sdim (AM.Index.getNode() && expandAddress(AM, false))) 543251607Sdim continue; 544251607Sdim 545251607Sdim // Reject cases where it isn't profitable to use LA(Y). 546251607Sdim if (AM.Form == SystemZAddressingMode::FormBDXLA && 547251607Sdim !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) 548251607Sdim return false; 549251607Sdim 550251607Sdim // Reject cases where the other instruction in a pair should be used. 551251607Sdim if (!isValidDisp(AM.DR, AM.Disp)) 552251607Sdim return false; 553251607Sdim 554251607Sdim // Make sure that ADJDYNALLOC is included where necessary. 555251607Sdim if (AM.isDynAlloc() && !AM.IncludesDynAlloc) 556251607Sdim return false; 557251607Sdim 558251607Sdim DEBUG(AM.dump()); 559251607Sdim return true; 560251607Sdim} 561251607Sdim 562251607Sdim// Insert a node into the DAG at least before Pos. This will reposition 563251607Sdim// the node as needed, and will assign it a node ID that is <= Pos's ID. 564251607Sdim// Note that this does *not* preserve the uniqueness of node IDs! 565251607Sdim// The selection DAG must no longer depend on their uniqueness when this 566251607Sdim// function is used. 567251607Sdimstatic void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { 568251607Sdim if (N.getNode()->getNodeId() == -1 || 569251607Sdim N.getNode()->getNodeId() > Pos->getNodeId()) { 570251607Sdim DAG->RepositionNode(Pos, N.getNode()); 571251607Sdim N.getNode()->setNodeId(Pos->getNodeId()); 572251607Sdim } 573251607Sdim} 574251607Sdim 575251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 576251607Sdim EVT VT, SDValue &Base, 577263509Sdim SDValue &Disp) const { 578251607Sdim Base = AM.Base; 579251607Sdim if (!Base.getNode()) 580251607Sdim // Register 0 means "no base". This is mostly useful for shifts. 581251607Sdim Base = CurDAG->getRegister(0, VT); 582251607Sdim else if (Base.getOpcode() == ISD::FrameIndex) { 583251607Sdim // Lower a FrameIndex to a TargetFrameIndex. 584251607Sdim int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 585251607Sdim Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 586251607Sdim } else if (Base.getValueType() != VT) { 587251607Sdim // Truncate values from i64 to i32, for shifts. 588251607Sdim assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && 589251607Sdim "Unexpected truncation"); 590263509Sdim SDLoc DL(Base); 591251607Sdim SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 592251607Sdim insertDAGNode(CurDAG, Base.getNode(), Trunc); 593251607Sdim Base = Trunc; 594251607Sdim } 595251607Sdim 596251607Sdim // Lower the displacement to a TargetConstant. 597251607Sdim Disp = CurDAG->getTargetConstant(AM.Disp, VT); 598251607Sdim} 599251607Sdim 600251607Sdimvoid SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 601251607Sdim EVT VT, SDValue &Base, 602263509Sdim SDValue &Disp, 603263509Sdim SDValue &Index) const { 604251607Sdim getAddressOperands(AM, VT, Base, Disp); 605251607Sdim 606251607Sdim Index = AM.Index; 607251607Sdim if (!Index.getNode()) 608251607Sdim // Register 0 means "no index". 609251607Sdim Index = CurDAG->getRegister(0, VT); 610251607Sdim} 611251607Sdim 612251607Sdimbool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR, 613251607Sdim SDValue Addr, SDValue &Base, 614263509Sdim SDValue &Disp) const { 615251607Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR); 616251607Sdim if (!selectAddress(Addr, AM)) 617251607Sdim return false; 618251607Sdim 619251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 620251607Sdim return true; 621251607Sdim} 622251607Sdim 623263509Sdimbool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR, 624263509Sdim SDValue Addr, SDValue &Base, 625263509Sdim SDValue &Disp) const { 626263509Sdim SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR); 627263509Sdim if (!selectAddress(Addr, AM) || AM.Index.getNode()) 628263509Sdim return false; 629263509Sdim 630263509Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp); 631263509Sdim return true; 632263509Sdim} 633263509Sdim 634251607Sdimbool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form, 635251607Sdim SystemZAddressingMode::DispRange DR, 636251607Sdim SDValue Addr, SDValue &Base, 637263509Sdim SDValue &Disp, SDValue &Index) const { 638251607Sdim SystemZAddressingMode AM(Form, DR); 639251607Sdim if (!selectAddress(Addr, AM)) 640251607Sdim return false; 641251607Sdim 642251607Sdim getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index); 643251607Sdim return true; 644251607Sdim} 645251607Sdim 646263509Sdimbool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op, 647263509Sdim uint64_t InsertMask) const { 648263509Sdim // We're only interested in cases where the insertion is into some operand 649263509Sdim // of Op, rather than into Op itself. The only useful case is an AND. 650263509Sdim if (Op.getOpcode() != ISD::AND) 651263509Sdim return false; 652263509Sdim 653263509Sdim // We need a constant mask. 654263509Sdim ConstantSDNode *MaskNode = 655263509Sdim dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode()); 656263509Sdim if (!MaskNode) 657263509Sdim return false; 658263509Sdim 659263509Sdim // It's not an insertion of Op.getOperand(0) if the two masks overlap. 660263509Sdim uint64_t AndMask = MaskNode->getZExtValue(); 661263509Sdim if (InsertMask & AndMask) 662263509Sdim return false; 663263509Sdim 664263509Sdim // It's only an insertion if all bits are covered or are known to be zero. 665263509Sdim // The inner check covers all cases but is more expensive. 666263509Sdim uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); 667263509Sdim if (Used != (AndMask | InsertMask)) { 668263509Sdim APInt KnownZero, KnownOne; 669263509Sdim CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne); 670263509Sdim if (Used != (AndMask | InsertMask | KnownZero.getZExtValue())) 671263509Sdim return false; 672263509Sdim } 673263509Sdim 674263509Sdim Op = Op.getOperand(0); 675263509Sdim return true; 676263509Sdim} 677263509Sdim 678263509Sdimbool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, 679263509Sdim uint64_t Mask) const { 680263509Sdim const SystemZInstrInfo *TII = getInstrInfo(); 681263509Sdim if (RxSBG.Rotate != 0) 682263509Sdim Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); 683263509Sdim Mask &= RxSBG.Mask; 684263509Sdim if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { 685263509Sdim RxSBG.Mask = Mask; 686263509Sdim return true; 687263509Sdim } 688263509Sdim return false; 689263509Sdim} 690263509Sdim 691263509Sdim// Return true if any bits of (RxSBG.Input & Mask) are significant. 692263509Sdimstatic bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) { 693263509Sdim // Rotate the mask in the same way as RxSBG.Input is rotated. 694263509Sdim if (RxSBG.Rotate != 0) 695263509Sdim Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); 696263509Sdim return (Mask & RxSBG.Mask) != 0; 697263509Sdim} 698263509Sdim 699263509Sdimbool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { 700263509Sdim SDValue N = RxSBG.Input; 701263509Sdim unsigned Opcode = N.getOpcode(); 702263509Sdim switch (Opcode) { 703263509Sdim case ISD::AND: { 704263509Sdim if (RxSBG.Opcode == SystemZ::RNSBG) 705263509Sdim return false; 706263509Sdim 707263509Sdim ConstantSDNode *MaskNode = 708263509Sdim dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 709263509Sdim if (!MaskNode) 710263509Sdim return false; 711263509Sdim 712263509Sdim SDValue Input = N.getOperand(0); 713263509Sdim uint64_t Mask = MaskNode->getZExtValue(); 714263509Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 715263509Sdim // If some bits of Input are already known zeros, those bits will have 716263509Sdim // been removed from the mask. See if adding them back in makes the 717263509Sdim // mask suitable. 718263509Sdim APInt KnownZero, KnownOne; 719263509Sdim CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); 720263509Sdim Mask |= KnownZero.getZExtValue(); 721263509Sdim if (!refineRxSBGMask(RxSBG, Mask)) 722263509Sdim return false; 723263509Sdim } 724263509Sdim RxSBG.Input = Input; 725263509Sdim return true; 726263509Sdim } 727263509Sdim 728263509Sdim case ISD::OR: { 729263509Sdim if (RxSBG.Opcode != SystemZ::RNSBG) 730263509Sdim return false; 731263509Sdim 732263509Sdim ConstantSDNode *MaskNode = 733263509Sdim dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 734263509Sdim if (!MaskNode) 735263509Sdim return false; 736263509Sdim 737263509Sdim SDValue Input = N.getOperand(0); 738263509Sdim uint64_t Mask = ~MaskNode->getZExtValue(); 739263509Sdim if (!refineRxSBGMask(RxSBG, Mask)) { 740263509Sdim // If some bits of Input are already known ones, those bits will have 741263509Sdim // been removed from the mask. See if adding them back in makes the 742263509Sdim // mask suitable. 743263509Sdim APInt KnownZero, KnownOne; 744263509Sdim CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); 745263509Sdim Mask &= ~KnownOne.getZExtValue(); 746263509Sdim if (!refineRxSBGMask(RxSBG, Mask)) 747263509Sdim return false; 748263509Sdim } 749263509Sdim RxSBG.Input = Input; 750263509Sdim return true; 751263509Sdim } 752263509Sdim 753263509Sdim case ISD::ROTL: { 754263509Sdim // Any 64-bit rotate left can be merged into the RxSBG. 755263509Sdim if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64) 756263509Sdim return false; 757263509Sdim ConstantSDNode *CountNode 758263509Sdim = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 759263509Sdim if (!CountNode) 760263509Sdim return false; 761263509Sdim 762263509Sdim RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; 763263509Sdim RxSBG.Input = N.getOperand(0); 764263509Sdim return true; 765263509Sdim } 766263509Sdim 767263509Sdim case ISD::SIGN_EXTEND: 768263509Sdim case ISD::ZERO_EXTEND: 769263509Sdim case ISD::ANY_EXTEND: { 770263509Sdim // Check that the extension bits are don't-care (i.e. are masked out 771263509Sdim // by the final mask). 772263509Sdim unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); 773263509Sdim if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize))) 774263509Sdim return false; 775263509Sdim 776263509Sdim RxSBG.Input = N.getOperand(0); 777263509Sdim return true; 778263509Sdim } 779263509Sdim 780263509Sdim case ISD::SHL: { 781263509Sdim ConstantSDNode *CountNode = 782263509Sdim dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 783263509Sdim if (!CountNode) 784263509Sdim return false; 785263509Sdim 786263509Sdim uint64_t Count = CountNode->getZExtValue(); 787263509Sdim unsigned BitSize = N.getValueType().getSizeInBits(); 788263509Sdim if (Count < 1 || Count >= BitSize) 789263509Sdim return false; 790263509Sdim 791263509Sdim if (RxSBG.Opcode == SystemZ::RNSBG) { 792263509Sdim // Treat (shl X, count) as (rotl X, size-count) as long as the bottom 793263509Sdim // count bits from RxSBG.Input are ignored. 794263509Sdim if (maskMatters(RxSBG, allOnes(Count))) 795263509Sdim return false; 796263509Sdim } else { 797263509Sdim // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 798263509Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count)) 799263509Sdim return false; 800263509Sdim } 801263509Sdim 802263509Sdim RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; 803263509Sdim RxSBG.Input = N.getOperand(0); 804263509Sdim return true; 805263509Sdim } 806263509Sdim 807263509Sdim case ISD::SRL: 808263509Sdim case ISD::SRA: { 809263509Sdim ConstantSDNode *CountNode = 810263509Sdim dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 811263509Sdim if (!CountNode) 812263509Sdim return false; 813263509Sdim 814263509Sdim uint64_t Count = CountNode->getZExtValue(); 815263509Sdim unsigned BitSize = N.getValueType().getSizeInBits(); 816263509Sdim if (Count < 1 || Count >= BitSize) 817263509Sdim return false; 818263509Sdim 819263509Sdim if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { 820263509Sdim // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top 821263509Sdim // count bits from RxSBG.Input are ignored. 822263509Sdim if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count))) 823263509Sdim return false; 824263509Sdim } else { 825263509Sdim // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), 826263509Sdim // which is similar to SLL above. 827263509Sdim if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count))) 828263509Sdim return false; 829263509Sdim } 830263509Sdim 831263509Sdim RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; 832263509Sdim RxSBG.Input = N.getOperand(0); 833263509Sdim return true; 834263509Sdim } 835263509Sdim default: 836263509Sdim return false; 837263509Sdim } 838263509Sdim} 839263509Sdim 840263509SdimSDValue SystemZDAGToDAGISel::getUNDEF(SDLoc DL, EVT VT) const { 841263509Sdim SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT); 842263509Sdim return SDValue(N, 0); 843263509Sdim} 844263509Sdim 845263509SdimSDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) const { 846263509Sdim if (N.getValueType() == MVT::i32 && VT == MVT::i64) 847263509Sdim return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, 848263509Sdim DL, VT, getUNDEF(DL, MVT::i64), N); 849263509Sdim if (N.getValueType() == MVT::i64 && VT == MVT::i32) 850263509Sdim return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); 851263509Sdim assert(N.getValueType() == VT && "Unexpected value types"); 852263509Sdim return N; 853263509Sdim} 854263509Sdim 855263509SdimSDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { 856263509Sdim EVT VT = N->getValueType(0); 857263509Sdim RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); 858263509Sdim unsigned Count = 0; 859263509Sdim while (expandRxSBG(RISBG)) 860263509Sdim if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND) 861263509Sdim Count += 1; 862263509Sdim if (Count == 0) 863263509Sdim return 0; 864263509Sdim if (Count == 1) { 865263509Sdim // Prefer to use normal shift instructions over RISBG, since they can handle 866263509Sdim // all cases and are sometimes shorter. 867263509Sdim if (N->getOpcode() != ISD::AND) 868263509Sdim return 0; 869263509Sdim 870263509Sdim // Prefer register extensions like LLC over RISBG. Also prefer to start 871263509Sdim // out with normal ANDs if one instruction would be enough. We can convert 872263509Sdim // these ANDs into an RISBG later if a three-address instruction is useful. 873263509Sdim if (VT == MVT::i32 || 874263509Sdim RISBG.Mask == 0xff || 875263509Sdim RISBG.Mask == 0xffff || 876263509Sdim SystemZ::isImmLF(~RISBG.Mask) || 877263509Sdim SystemZ::isImmHF(~RISBG.Mask)) { 878263509Sdim // Force the new mask into the DAG, since it may include known-one bits. 879263509Sdim ConstantSDNode *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode()); 880263509Sdim if (MaskN->getZExtValue() != RISBG.Mask) { 881263509Sdim SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT); 882263509Sdim N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask); 883263509Sdim return SelectCode(N); 884263509Sdim } 885263509Sdim return 0; 886263509Sdim } 887263509Sdim } 888263509Sdim 889263509Sdim unsigned Opcode = SystemZ::RISBG; 890263509Sdim EVT OpcodeVT = MVT::i64; 891263509Sdim if (VT == MVT::i32 && Subtarget.hasHighWord()) { 892263509Sdim Opcode = SystemZ::RISBMux; 893263509Sdim OpcodeVT = MVT::i32; 894263509Sdim RISBG.Start &= 31; 895263509Sdim RISBG.End &= 31; 896263509Sdim } 897263509Sdim SDValue Ops[5] = { 898263509Sdim getUNDEF(SDLoc(N), OpcodeVT), 899263509Sdim convertTo(SDLoc(N), OpcodeVT, RISBG.Input), 900263509Sdim CurDAG->getTargetConstant(RISBG.Start, MVT::i32), 901263509Sdim CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32), 902263509Sdim CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32) 903263509Sdim }; 904263509Sdim N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops); 905263509Sdim return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 906263509Sdim} 907263509Sdim 908263509SdimSDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { 909263509Sdim // Try treating each operand of N as the second operand of the RxSBG 910263509Sdim // and see which goes deepest. 911263509Sdim RxSBGOperands RxSBG[] = { 912263509Sdim RxSBGOperands(Opcode, N->getOperand(0)), 913263509Sdim RxSBGOperands(Opcode, N->getOperand(1)) 914263509Sdim }; 915263509Sdim unsigned Count[] = { 0, 0 }; 916263509Sdim for (unsigned I = 0; I < 2; ++I) 917263509Sdim while (expandRxSBG(RxSBG[I])) 918263509Sdim if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND) 919263509Sdim Count[I] += 1; 920263509Sdim 921263509Sdim // Do nothing if neither operand is suitable. 922263509Sdim if (Count[0] == 0 && Count[1] == 0) 923263509Sdim return 0; 924263509Sdim 925263509Sdim // Pick the deepest second operand. 926263509Sdim unsigned I = Count[0] > Count[1] ? 0 : 1; 927263509Sdim SDValue Op0 = N->getOperand(I ^ 1); 928263509Sdim 929263509Sdim // Prefer IC for character insertions from memory. 930263509Sdim if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0) 931263509Sdim if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode())) 932263509Sdim if (Load->getMemoryVT() == MVT::i8) 933263509Sdim return 0; 934263509Sdim 935263509Sdim // See whether we can avoid an AND in the first operand by converting 936263509Sdim // ROSBG to RISBG. 937263509Sdim if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) 938263509Sdim Opcode = SystemZ::RISBG; 939263509Sdim 940263509Sdim EVT VT = N->getValueType(0); 941263509Sdim SDValue Ops[5] = { 942263509Sdim convertTo(SDLoc(N), MVT::i64, Op0), 943263509Sdim convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input), 944263509Sdim CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32), 945263509Sdim CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32), 946263509Sdim CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32) 947263509Sdim }; 948263509Sdim N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops); 949263509Sdim return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 950263509Sdim} 951263509Sdim 952251607SdimSDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, 953251607Sdim SDValue Op0, uint64_t UpperVal, 954251607Sdim uint64_t LowerVal) { 955251607Sdim EVT VT = Node->getValueType(0); 956263509Sdim SDLoc DL(Node); 957251607Sdim SDValue Upper = CurDAG->getConstant(UpperVal, VT); 958251607Sdim if (Op0.getNode()) 959251607Sdim Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); 960251607Sdim Upper = SDValue(Select(Upper.getNode()), 0); 961251607Sdim 962251607Sdim SDValue Lower = CurDAG->getConstant(LowerVal, VT); 963251607Sdim SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); 964251607Sdim return Or.getNode(); 965251607Sdim} 966251607Sdim 967263509Sdimbool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store, 968263509Sdim LoadSDNode *Load) const { 969263509Sdim // Check that the two memory operands have the same size. 970263509Sdim if (Load->getMemoryVT() != Store->getMemoryVT()) 971263509Sdim return false; 972263509Sdim 973263509Sdim // Volatility stops an access from being decomposed. 974263509Sdim if (Load->isVolatile() || Store->isVolatile()) 975263509Sdim return false; 976263509Sdim 977263509Sdim // There's no chance of overlap if the load is invariant. 978263509Sdim if (Load->isInvariant()) 979263509Sdim return true; 980263509Sdim 981263509Sdim // Otherwise we need to check whether there's an alias. 982263509Sdim const Value *V1 = Load->getSrcValue(); 983263509Sdim const Value *V2 = Store->getSrcValue(); 984263509Sdim if (!V1 || !V2) 985263509Sdim return false; 986263509Sdim 987263509Sdim // Reject equality. 988263509Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 989263509Sdim int64_t End1 = Load->getSrcValueOffset() + Size; 990263509Sdim int64_t End2 = Store->getSrcValueOffset() + Size; 991263509Sdim if (V1 == V2 && End1 == End2) 992263509Sdim return false; 993263509Sdim 994263509Sdim return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()), 995263509Sdim AliasAnalysis::Location(V2, End2, Store->getTBAAInfo())); 996263509Sdim} 997263509Sdim 998263509Sdimbool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const { 999263509Sdim StoreSDNode *Store = cast<StoreSDNode>(N); 1000263509Sdim LoadSDNode *Load = cast<LoadSDNode>(Store->getValue()); 1001263509Sdim 1002263509Sdim // Prefer not to use MVC if either address can use ... RELATIVE LONG 1003263509Sdim // instructions. 1004263509Sdim uint64_t Size = Load->getMemoryVT().getStoreSize(); 1005263509Sdim if (Size > 1 && Size <= 8) { 1006263509Sdim // Prefer LHRL, LRL and LGRL. 1007263509Sdim if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) 1008263509Sdim return false; 1009263509Sdim // Prefer STHRL, STRL and STGRL. 1010263509Sdim if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) 1011263509Sdim return false; 1012263509Sdim } 1013263509Sdim 1014263509Sdim return canUseBlockOperation(Store, Load); 1015263509Sdim} 1016263509Sdim 1017263509Sdimbool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N, 1018263509Sdim unsigned I) const { 1019263509Sdim StoreSDNode *StoreA = cast<StoreSDNode>(N); 1020263509Sdim LoadSDNode *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I)); 1021263509Sdim LoadSDNode *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I)); 1022263509Sdim return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB); 1023263509Sdim} 1024263509Sdim 1025251607SdimSDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { 1026251607Sdim // Dump information about the Node being selected 1027251607Sdim DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 1028251607Sdim 1029251607Sdim // If we have a custom node, we already have selected! 1030251607Sdim if (Node->isMachineOpcode()) { 1031251607Sdim DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 1032255946Sdim Node->setNodeId(-1); 1033251607Sdim return 0; 1034251607Sdim } 1035251607Sdim 1036251607Sdim unsigned Opcode = Node->getOpcode(); 1037263509Sdim SDNode *ResNode = 0; 1038251607Sdim switch (Opcode) { 1039251607Sdim case ISD::OR: 1040263509Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1041263509Sdim ResNode = tryRxSBG(Node, SystemZ::ROSBG); 1042263509Sdim goto or_xor; 1043263509Sdim 1044251607Sdim case ISD::XOR: 1045263509Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1046263509Sdim ResNode = tryRxSBG(Node, SystemZ::RXSBG); 1047263509Sdim // Fall through. 1048263509Sdim or_xor: 1049251607Sdim // If this is a 64-bit operation in which both 32-bit halves are nonzero, 1050251607Sdim // split the operation into two. 1051263509Sdim if (!ResNode && Node->getValueType(0) == MVT::i64) 1052251607Sdim if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { 1053251607Sdim uint64_t Val = Op1->getZExtValue(); 1054251607Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) 1055251607Sdim Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0), 1056251607Sdim Val - uint32_t(Val), uint32_t(Val)); 1057251607Sdim } 1058251607Sdim break; 1059251607Sdim 1060263509Sdim case ISD::AND: 1061263509Sdim if (Node->getOperand(1).getOpcode() != ISD::Constant) 1062263509Sdim ResNode = tryRxSBG(Node, SystemZ::RNSBG); 1063263509Sdim // Fall through. 1064263509Sdim case ISD::ROTL: 1065263509Sdim case ISD::SHL: 1066263509Sdim case ISD::SRL: 1067263509Sdim if (!ResNode) 1068263509Sdim ResNode = tryRISBGZero(Node); 1069263509Sdim break; 1070263509Sdim 1071251607Sdim case ISD::Constant: 1072251607Sdim // If this is a 64-bit constant that is out of the range of LLILF, 1073251607Sdim // LLIHF and LGFI, split it into two 32-bit pieces. 1074251607Sdim if (Node->getValueType(0) == MVT::i64) { 1075251607Sdim uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue(); 1076251607Sdim if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) 1077251607Sdim Node = splitLargeImmediate(ISD::OR, Node, SDValue(), 1078251607Sdim Val - uint32_t(Val), uint32_t(Val)); 1079251607Sdim } 1080251607Sdim break; 1081251607Sdim 1082251607Sdim case ISD::ATOMIC_LOAD_SUB: 1083251607Sdim // Try to convert subtractions of constants to additions. 1084251607Sdim if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 1085251607Sdim uint64_t Value = -Op2->getZExtValue(); 1086251607Sdim EVT VT = Node->getValueType(0); 1087251607Sdim if (VT == MVT::i32 || isInt<32>(Value)) { 1088251607Sdim SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1), 1089251607Sdim CurDAG->getConstant(int32_t(Value), VT) }; 1090251607Sdim Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD, 1091251607Sdim Node->getVTList(), Ops, array_lengthof(Ops)); 1092251607Sdim } 1093251607Sdim } 1094251607Sdim break; 1095263509Sdim 1096263509Sdim case SystemZISD::SELECT_CCMASK: { 1097263509Sdim SDValue Op0 = Node->getOperand(0); 1098263509Sdim SDValue Op1 = Node->getOperand(1); 1099263509Sdim // Prefer to put any load first, so that it can be matched as a 1100263509Sdim // conditional load. 1101263509Sdim if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) { 1102263509Sdim SDValue CCValid = Node->getOperand(2); 1103263509Sdim SDValue CCMask = Node->getOperand(3); 1104263509Sdim uint64_t ConstCCValid = 1105263509Sdim cast<ConstantSDNode>(CCValid.getNode())->getZExtValue(); 1106263509Sdim uint64_t ConstCCMask = 1107263509Sdim cast<ConstantSDNode>(CCMask.getNode())->getZExtValue(); 1108263509Sdim // Invert the condition. 1109263509Sdim CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, 1110263509Sdim CCMask.getValueType()); 1111263509Sdim SDValue Op4 = Node->getOperand(4); 1112263509Sdim Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); 1113263509Sdim } 1114263509Sdim break; 1115251607Sdim } 1116263509Sdim } 1117251607Sdim 1118251607Sdim // Select the default instruction 1119263509Sdim if (!ResNode) 1120263509Sdim ResNode = SelectCode(Node); 1121251607Sdim 1122251607Sdim DEBUG(errs() << "=> "; 1123251607Sdim if (ResNode == NULL || ResNode == Node) 1124251607Sdim Node->dump(CurDAG); 1125251607Sdim else 1126251607Sdim ResNode->dump(CurDAG); 1127251607Sdim errs() << "\n"; 1128251607Sdim ); 1129251607Sdim return ResNode; 1130251607Sdim} 1131251607Sdim 1132251607Sdimbool SystemZDAGToDAGISel:: 1133251607SdimSelectInlineAsmMemoryOperand(const SDValue &Op, 1134251607Sdim char ConstraintCode, 1135251607Sdim std::vector<SDValue> &OutOps) { 1136251607Sdim assert(ConstraintCode == 'm' && "Unexpected constraint code"); 1137251607Sdim // Accept addresses with short displacements, which are compatible 1138251607Sdim // with Q, R, S and T. But keep the index operand for future expansion. 1139251607Sdim SDValue Base, Disp, Index; 1140251607Sdim if (!selectBDXAddr(SystemZAddressingMode::FormBD, 1141251607Sdim SystemZAddressingMode::Disp12Only, 1142251607Sdim Op, Base, Disp, Index)) 1143251607Sdim return true; 1144251607Sdim OutOps.push_back(Base); 1145251607Sdim OutOps.push_back(Disp); 1146251607Sdim OutOps.push_back(Index); 1147251607Sdim return false; 1148251607Sdim} 1149