Searched refs:Op0 (Results 1 - 25 of 60) sorted by relevance

123

/freebsd-9.3-release/contrib/llvm/lib/Analysis/
H A DInstructionSimplify.cpp137 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS))
138 if (Op0->getOpcode() == OpcodeToExpand) {
140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS;
197 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS);
200 if (!Op0 || Op0->getOpcode() != OpcodeToExtract ||
205 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1);
268 BinaryOperator *Op0
592 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
653 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
734 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
859 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
868 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
910 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
946 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
974 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1037 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1043 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1049 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1057 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1065 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1137 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1145 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1153 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1161 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1167 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument
1180 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1188 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1242 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1250 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1258 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1266 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1272 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument
1285 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1293 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1337 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
1353 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1362 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument
1384 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1394 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument
1420 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1430 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1521 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1529 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1615 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1623 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1675 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
[all...]
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DFastISel.h191 unsigned Op0, bool Op0IsKill);
198 unsigned Op0, bool Op0IsKill,
207 unsigned Op0, bool Op0IsKill,
216 unsigned Op0, bool Op0IsKill,
225 unsigned Op0, bool Op0IsKill,
236 unsigned Op0, bool Op0IsKill,
263 unsigned Op0, bool Op0IsKill);
269 unsigned Op0, bool Op0IsKill,
276 unsigned Op0, bool Op0IsKill,
284 unsigned Op0, boo
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp119 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
121 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
128 return BinaryOperator::CreateNeg(Op0, I.getName());
163 if (Op0->hasOneUse() &&
164 match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) {
178 if (Op0->hasOneUse()) {
181 if (match(Op0, m_Sub(m_Value(Y), m_Value(X))))
183 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1))))
197 if (SelectInst *SI = dyn_cast<SelectInst>(Op0))
201 if (isa<PHINode>(Op0))
407 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
674 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
767 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
777 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
786 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
808 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument
847 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
908 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
989 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1114 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1146 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1178 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1249 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
[all...]
H A DInstCombineShifts.cpp24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
31 if (isa<Constant>(Op0))
37 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, argument
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
322 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
331 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
338 return ReplaceInstUsesWith(I, Constant::getNullValue(Op0->getType()));
345 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
[all...]
H A DInstCombineCompares.cpp2049 /// \brief Check if the order of \p Op0 and \p Op1 as operand in an ICmpInst
2056 /// \return true if Op0 and Op1 should be swapped.
2057 static bool swapMayExposeCSEOpportunities(const Value * Op0, argument
2061 if (Op0->getType()->isPointerTy())
2063 // Count every uses of both Op0 and Op1 in a subtract.
2064 // Each time Op0 is the first operand, count -1: swapping is bad, the
2066 // Each time Op0 is the second operand, count +1: swapping is good, the
2068 // At the end, if the benefit is greater than 0, Op0 should come second to
2071 for (Value::const_use_iterator UI = Op0->use_begin(), UIEnd = Op0
2092 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
3230 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
[all...]
H A DInstCombineAndOrXor.cpp794 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local
797 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
1100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1102 if (Value *V = SimplifyAndInst(Op0, Op1, TD))
1118 if (BinaryOperator *Op0I = dyn_cast<BinaryOperator>(Op0)) {
1197 if (match(Op0, m_Trunc(m_And(m_Value(X), m_ConstantInt(YC))))) {
1210 if (SelectInst *SI = dyn_cast<SelectInst>(Op0))
1213 if (isa<PHINode>(Op0))
1220 if (Value *Op0NotVal = dyn_castNotVal(Op0))
1222 if (Op0
1607 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local
1918 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
2250 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
2482 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local
[all...]
H A DInstCombineAddSub.cpp1353 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1355 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
1365 BinaryOperator *Res = BinaryOperator::CreateAdd(Op0, V);
1372 return BinaryOperator::CreateXor(Op0, Op1);
1375 if (match(Op0, m_AllOnes()))
1378 if (ConstantInt *C = dyn_cast<ConstantInt>(Op0)) {
1426 if (match(Op1, m_Add(m_Specific(Op0), m_Value(Y))) ||
1427 match(Op1, m_Add(m_Value(Y), m_Specific(Op0))))
1431 if (match(Op0, m_Sub(m_Specific(Op1), m_Value(Y))))
1442 return BinaryOperator::CreateAdd(Op0,
1521 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
[all...]
H A DInstructionCombining.cpp213 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); local
218 if (Op0 && Op0->getOpcode() == Opcode) {
219 Value *A = Op0->getOperand(0);
220 Value *B = Op0->getOperand(1);
231 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) {
233 // the operands to Op0.
269 if (Op0
398 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); local
565 Value *Op0 = SO, *Op1 = ConstOperand; local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp398 unsigned Op0 = getRegForValue(I->getOperand(0)); local
399 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
423 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
435 ISDOpcode, Op0, Op0IsKill, CF);
453 Op0, Op0IsKill,
786 unsigned Op0 = getRegForValue(I->getOperand(0)); local
787 if (Op0 == 0)
802 ResultReg).addReg(Op0);
808 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
950 const Value *Op0 local
1165 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1216 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1235 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1256 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1280 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1301 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1324 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
1345 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1369 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument
1426 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument
1442 FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument
[all...]
H A DTargetLowering.cpp1421 SDValue Op0 = N0; local
1422 if (Op0.getOpcode() == ISD::TRUNCATE)
1423 Op0 = Op0.getOperand(0);
1425 if ((Op0.getOpcode() == ISD::XOR) &&
1426 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1427 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1430 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1433 if (Op0
[all...]
/freebsd-9.3-release/contrib/llvm/include/llvm/Support/
H A DGetElementPtrTypeIterator.h102 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument
103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin());
108 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
H A DPatternMatch.h1089 m_Intrinsic(const T0 &Op0) { argument
1090 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
1095 m_Intrinsic(const T0 &Op0, const T1 &Op1) { argument
1096 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
1101 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument
1102 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1107 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument
1108 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
1114 m_BSwap(const Opnd0 &Op0) { argument
1115 return m_Intrinsic<Intrinsic::bswap>(Op0);
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp202 SDValue Op0, Op1; local
206 if (!SelectADDRrr(Op, Op0, Op1))
207 SelectADDRri(Op, Op0, Op1);
211 OutOps.push_back(Op0);
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp284 // If Op0 is null, then Node is a constant that can be loaded using:
288 // If Op0 is nonnull, then Node can be implemented using:
290 // (Opcode (Opcode Op0 UpperVal) LowerVal)
291 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
399 SDValue Op0, uint64_t Op1) {
403 changeComponent(AM, IsBase, Op0);
422 SDValue Op0 = N.getOperand(0); local
425 unsigned Op0Code = Op0->getOpcode();
431 return expandAdjDynAlloc(AM, IsBase, Op0);
398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument
927 SDValue Op0 = N->getOperand(I ^ 1); local
952 splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, uint64_t UpperVal, uint64_t LowerVal) argument
1097 SDValue Op0 = Node->getOperand(0); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1166 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1168 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1176 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1181 moveToTop(Op0, I); // Move dead operand to TOS.
1182 TOS = Op0;
1192 duplicateToTop(Op0, Dest, I);
1193 Op0 = TOS = Dest;
1200 duplicateToTop(Op0, Dest, I);
1201 Op0 = TOS = Dest;
1207 assert((TOS == Op0 || TO
[all...]
/freebsd-9.3-release/contrib/llvm/include/llvm/Analysis/
H A DInstructionSimplify.h128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
H A DScalarEvolution.h589 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
592 Ops.push_back(Op0);
607 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
610 Ops.push_back(Op0);
/freebsd-9.3-release/contrib/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp163 Value *Op0 = C->getOperand(0); local
164 if (isa<Instruction>(Op0) &&
165 cast<Instruction>(Op0)->getParent() == C->getParent())
/freebsd-9.3-release/contrib/llvm/lib/ExecutionEngine/
H A DExecutionEngine.cpp588 Constant *Op0 = CE->getOperand(0); local
592 GenericValue Result = getConstantValue(Op0);
601 GenericValue GV = getConstantValue(Op0);
607 GenericValue GV = getConstantValue(Op0);
613 GenericValue GV = getConstantValue(Op0);
620 GenericValue GV = getConstantValue(Op0);
626 GenericValue GV = getConstantValue(Op0);
631 GenericValue GV = getConstantValue(Op0);
646 GenericValue GV = getConstantValue(Op0);
662 GenericValue GV = getConstantValue(Op0);
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp109 unsigned Op0, bool Op0IsKill);
112 unsigned Op0, bool Op0IsKill,
116 unsigned Op0, bool Op0IsKill,
121 unsigned Op0, bool Op0IsKill,
125 unsigned Op0, bool Op0IsKill,
129 unsigned Op0, bool Op0IsKill,
140 unsigned Op0, bool Op0IsKill,
324 unsigned Op0, bool Op0IsKill) {
330 Op0 = constrainOperandRegClass(II, Op0,
322 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
344 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
371 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
402 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
427 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
452 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
520 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument
1263 Value *Op0 = I->getOperand(0); local
[all...]
H A DARMLoadStoreOptimizer.cpp1560 bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
1638 /// Copy Op0 and Op1 operands into a new array assigned to MI.
1639 static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0, argument
1642 size_t numMemRefs = (Op0->memoperands_end() - Op0->memoperands_begin())
1648 std::copy(Op0->memoperands_begin(), Op0->memoperands_end(), MemBegin);
1655 ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, argument
1668 unsigned Opcode = Op0->getOpcode();
1687 if (!Op0
1818 MachineInstr *Op0 = Ops.back(); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp455 SDValue Op0 = N->getOperand(0);
457 unsigned Op0Opcode = Op0->getOpcode();
475 SDValue Op0Op2 = Op0->getOperand(2);
482 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
483 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
484 Op0->getVTList(), Ops, Op0->getNumOperands());
485 return Op0;
575 SDValue Op0
723 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); local
730 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); local
801 SDValue Op0 = N->getOperand(0); local
899 SDValue Op0 = N->getOperand(0); local
947 SDValue Op0 = N->getOperand(0); local
2146 SDValue Op0 = Op->getOperand(0); local
2520 SDValue Op0; local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp247 MachineOperand &Op0 = MI->getOperand(0); local
248 unsigned Reg0 = Op0.getReg();
/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp289 SDValue Op0, Op1; local
293 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op0);
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp114 unsigned Op0, bool Op0IsKill,
118 unsigned Op0, bool Op0IsKill);
121 unsigned Op0, bool Op0IsKill,
652 Value *Op0 = I->getOperand(0); local
661 if (!isLoadTypeLegal(Op0->getType(), VT))
665 SrcReg = getRegForValue(Op0);
2182 unsigned Op0, bool Op0IsKill,
2185 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2187 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2194 Op0, Op0IsKil
2180 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
2200 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill) argument
2213 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
[all...]

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