Lines Matching refs:Op0
1421 SDValue Op0 = N0;
1422 if (Op0.getOpcode() == ISD::TRUNCATE)
1423 Op0 = Op0.getOperand(0);
1425 if ((Op0.getOpcode() == ISD::XOR) &&
1426 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1427 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1430 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1433 if (Op0.getOpcode() == ISD::AND &&
1434 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1435 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1437 if (Op0.getValueType().bitsGT(VT))
1438 Op0 = DAG.getNode(ISD::AND, dl, VT,
1439 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1441 else if (Op0.getValueType().bitsLT(VT))
1442 Op0 = DAG.getNode(ISD::AND, dl, VT,
1443 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1446 return DAG.getSetCC(dl, VT, Op0,
1447 DAG.getConstant(0, Op0.getValueType()),
1450 if (Op0.getOpcode() == ISD::AssertZext &&
1451 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1452 return DAG.getSetCC(dl, VT, Op0,
1453 DAG.getConstant(0, Op0.getValueType()),