CodeGen/SelectionDAG/FastISel.cpp

398   unsigned Op0 = getRegForValue(I->getOperand(0));
399   if (Op0 == 0)   // Unhandled operand. Halt "fast" selection and bail.
423     unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
435                                      ISDOpcode, Op0, Op0IsKill, CF);
453                                    Op0, Op0IsKill,
786   unsigned Op0 = getRegForValue(I->getOperand(0));
787   if (Op0 == 0)
802               ResultReg).addReg(Op0);
808     ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
950   const Value *Op0 = EVI->getOperand(0);
951   Type *AggTy = Op0->getType();
955   DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
958   else if (isa<Instruction>(Op0))
959     ResultReg = FuncInfo.InitializeRegForValue(Op0);
1119                               unsigned /*Op0*/, bool /*Op0IsKill*/) {
1125                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1141                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1148                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1155                                 unsigned /*Op0*/, bool /*Op0IsKill*/,
1166                                 unsigned Op0, bool Op0IsKill,
1185   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1199                      Op0, Op0IsKill,
1218                                   unsigned Op0, bool Op0IsKill) {
1224       .addReg(Op0, Op0IsKill * RegState::Kill);
1227       .addReg(Op0, Op0IsKill * RegState::Kill);
1237                                    unsigned Op0, bool Op0IsKill,
1244       .addReg(Op0, Op0IsKill * RegState::Kill)
1248       .addReg(Op0, Op0IsKill * RegState::Kill)
1258                                    unsigned Op0, bool Op0IsKill,
1266       .addReg(Op0, Op0IsKill * RegState::Kill)
1271       .addReg(Op0, Op0IsKill * RegState::Kill)
1282                                    unsigned Op0, bool Op0IsKill,
1289       .addReg(Op0, Op0IsKill * RegState::Kill)
1293       .addReg(Op0, Op0IsKill * RegState::Kill)
1303                                    unsigned Op0, bool Op0IsKill,
1310       .addReg(Op0, Op0IsKill * RegState::Kill)
1315       .addReg(Op0, Op0IsKill * RegState::Kill)
1326                                    unsigned Op0, bool Op0IsKill,
1333       .addReg(Op0, Op0IsKill * RegState::Kill)
1337       .addReg(Op0, Op0IsKill * RegState::Kill)
1347                                     unsigned Op0, bool Op0IsKill,
1355       .addReg(Op0, Op0IsKill * RegState::Kill)
1360       .addReg(Op0, Op0IsKill * RegState::Kill)
1371                                      unsigned Op0, bool Op0IsKill,
1379       .addReg(Op0, Op0IsKill * RegState::Kill)
1384       .addReg(Op0, Op0IsKill * RegState::Kill)
1427                                               unsigned Op0, bool Op0IsKill,
1430   assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1432   const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1433   MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1436     .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1442 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1443   return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);