Searched refs:CSR_READ_2 (Results 1 - 25 of 63) sorted by relevance

123

/freebsd-9.3-release/sys/dev/sn/
H A Dif_sn.c181 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
187 i = CSR_READ_2(sc, CONFIG_REG_W);
198 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
294 flags = CSR_READ_2(sc, CONFIG_REG_W);
303 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
570 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
682 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
842 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
875 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
893 tx_status = CSR_READ_2(s
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H A Dif_snreg.h403 #define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \
404 CSR_READ_2(sc, RECV_CONTROL_REG_W); \
405 CSR_READ_2(sc, RECV_CONTROL_REG_W); }
H A Dif_snvar.h59 #define CSR_READ_2(sc, off) (bus_read_2((sc)->port_res, off)) macro
/freebsd-9.3-release/sys/dev/vte/
H A Dif_vte.c180 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
189 return (CSR_READ_2(sc, VTE_MMRD));
205 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
361 mid = CSR_READ_2(sc, VTE_MID0L);
364 mid = CSR_READ_2(sc, VTE_MID0M);
367 mid = CSR_READ_2(sc, VTE_MID0H);
410 CSR_READ_2(sc, VTE_MACID));
411 macid = CSR_READ_2(sc, VTE_MACID_REV);
1237 mcr = CSR_READ_2(sc, VTE_MCR0);
1262 CSR_READ_2(s
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H A Dif_vtevar.h151 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-9.3-release/sys/dev/bm/
H A Dif_bm.c187 reg = CSR_READ_2(sc, BM_MII_CSR);
220 reg = CSR_READ_2(sc, BM_TX_CONFIG);
228 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
917 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
927 reg = CSR_READ_2(sc, BM_RX_CONFIG);
965 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
968 reg = CSR_READ_2(sc, BM_RX_CONFIG);
998 reg = CSR_READ_2(sc, BM_TX_RESET);
1006 reg = CSR_READ_2(sc, BM_TX_IFC);
1010 CSR_READ_2(s
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H A Dif_bmreg.h164 #define CSR_READ_2(sc, reg) \ macro
/freebsd-9.3-release/sys/dev/ep/
H A Dif_ep.c147 (*result) = CSR_READ_2(sc, EP_W0_EEPROM_DATA);
228 config = CSR_READ_2(sc, EP_W0_CONFIG_CTRL);
245 sc->ep_connector = CSR_READ_2(sc, EP_W0_ADDRESS_CFG) >> ACF_CONNECTOR_BITS;
517 if (CSR_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
521 if (CSR_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
573 if (CSR_READ_2(sc, EP_W1_RX_STATUS) & RX_BYTES_MASK) {
609 if (sc->gone || CSR_READ_2(sc, EP_STATUS) == 0xffff)
617 while ((status = CSR_READ_2(sc, EP_STATUS)) & S_5_INTS) {
629 CSR_READ_2(sc, EP_W1_FREE_TX);
638 CSR_READ_2(s
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H A Dif_epreg.h62 #define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
318 #define EP_BUSY_WAIT(sc) while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS)
335 ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \
H A Dif_epvar.h87 #define CSR_READ_2(sc, off) (bus_space_read_2((sc)->bst, (sc)->bsh, off)) macro
/freebsd-9.3-release/sys/dev/vx/
H A Dif_vxvar.h69 #define CSR_READ_2(sc, reg) \ macro
H A Dif_vx.c186 x = CSR_READ_2(sc, VX_W0_EEPROM_DATA);
296 sc->vx_connectors = CSR_READ_2(sc, VX_W3_RESET_OPT) & 0x7f;
472 if (CSR_READ_2(sc, VX_W1_FREE_TX) < len + pad + 4) {
476 if (CSR_READ_2(sc, VX_W1_FREE_TX) < len + pad + 4) {
520 if ((CSR_READ_2(sc, VX_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) {
523 if ((CSR_READ_2(sc, VX_STATUS) & S_INTR_LATCH) == 0) {
567 fifost = CSR_READ_2(sc, VX_W4_FIFO_DIAG);
648 status = CSR_READ_2(sc, VX_STATUS);
696 len = CSR_READ_2(sc, VX_W1_RX_STATUS);
788 len = CSR_READ_2(s
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H A Dif_vx_pci.c165 if (!(CSR_READ_2(sc, VX_W0_EEPROM_DATA) & NO_RX_OVN_ANOMALY))
/freebsd-9.3-release/sys/dev/vge/
H A Dif_vgevar.h226 #define CSR_READ_2(sc, reg) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-9.3-release/sys/dev/ex/
H A Dif_ex.c540 i = CSR_READ_2(sc, IO_PORT_REG);
554 CSR_READ_2(sc, IO_PORT_REG);
680 if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))
683 tx_status = CSR_READ_2(sc, IO_PORT_REG);
684 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
730 while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
732 rx_status = CSR_READ_2(sc, IO_PORT_REG);
733 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
734 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
928 CSR_READ_2(s
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H A Dif_exvar.h96 #define CSR_READ_2(sc, off) (bus_read_2((sc)->ioport, off)) macro
/freebsd-9.3-release/sys/dev/ste/
H A Dif_ste.c190 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
193 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
282 cfg = CSR_READ_2(sc, STE_MACCTL0);
367 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
398 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
488 status = CSR_READ_2(sc, STE_ISR_ACK);
520 status = CSR_READ_2(sc, STE_ISR_ACK);
686 txstat = CSR_READ_2(sc, STE_TX_STATUS);
810 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
811 CSR_READ_2(s
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/freebsd-9.3-release/sys/dev/tx/
H A Dif_txvar.h138 #define CSR_READ_2(sc, reg) \ macro
/freebsd-9.3-release/sys/dev/wi/
H A Dif_wi_pci.c209 (CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
220 reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF);
223 "CSR_READ_2(WI_HFA384X_SWSUPPORT0_OFF) "
/freebsd-9.3-release/sys/dev/an/
H A Dif_an.c876 id = CSR_READ_2(sc, AN_RX_FID);
1136 id = CSR_READ_2(sc, AN_TX_CMP_FID(sc->mpi350));
1152 id = CSR_READ_2(sc, AN_TX_CMP_FID(sc->mpi350));
1235 status = CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350));
1243 if (CSR_READ_2(sc, AN_LINKSTAT(sc->mpi350))
1294 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) & AN_CMD_BUSY) {
1311 if (CSR_READ_2(sc, AN_EVENT_STAT(sc->mpi350)) & AN_EV_CMD)
1316 reply->an_resp0 = CSR_READ_2(sc, AN_RESP0(sc->mpi350));
1317 reply->an_resp1 = CSR_READ_2(sc, AN_RESP1(sc->mpi350));
1318 reply->an_resp2 = CSR_READ_2(s
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/freebsd-9.3-release/sys/dev/bwi/
H A Dif_bwivar.h77 #define CSR_READ_2(sc, reg) \ macro
88 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
93 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
98 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Dbwirf.c219 return CSR_READ_2(sc, BWI_RF_DATA_LO);
250 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
254 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
781 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
818 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
819 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1284 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1286 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1665 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1666 bbp_atten = CSR_READ_2(s
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/freebsd-9.3-release/sys/dev/fxp/
H A Dif_fxpvar.h244 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) macro
/freebsd-9.3-release/sys/dev/stge/
H A Dif_stge.c382 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
404 *data = CSR_READ_2(sc, STGE_EepromData);
542 v = CSR_READ_2(sc, STGE_StationAddress0);
545 v = CSR_READ_2(sc, STGE_StationAddress1);
548 v = CSR_READ_2(sc, STGE_StationAddress2);
1470 status = CSR_READ_2(sc, STGE_IntStatus);
1476 status = CSR_READ_2(sc, STGE_IntStatusAck);
1801 status = CSR_READ_2(sc, STGE_IntStatus);
1881 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1893 CSR_READ_2(s
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/freebsd-9.3-release/sys/dev/xl/
H A Dif_xl.c357 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
387 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
529 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
578 word = CSR_READ_2(sc, XL_W0_EE_DATA);
748 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
858 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
882 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1369 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
2164 status = CSR_READ_2(sc, XL_STATUS);
2251 status = CSR_READ_2(s
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