/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS) 28 : XCoreGenSubtargetInfo(TT, CPU, FS) 26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | XCoreSubtarget.h | 34 XCoreSubtarget(const std::string &TT, const std::string &CPU, 39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64Subtarget.cpp | 31 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) argument 32 : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false), 33 HasCrypto(false), TargetTriple(TT), CPUString(CPU) { 35 initializeSubtargetFeatures(CPU, FS); 38 void AArch64Subtarget::initializeSubtargetFeatures(StringRef CPU, argument 40 if (CPU.empty()) 52 ParseSubtargetFeatures(CPU, FullFS);
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H A D | AArch64Subtarget.h | 39 /// CPUString - String name of used CPU. 43 void initializeSubtargetFeatures(StringRef CPU, StringRef FS); 49 AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS); 57 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | AArch64TargetMachine.cpp | 30 StringRef CPU, StringRef FS, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS), 29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXSubtarget.cpp | 26 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, argument 28 : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0), 38 // Provide the default CPU if none 41 ParseSubtargetFeatures((CPU.empty() ? defCPU : CPU), FS); 44 if (FS.empty() && CPU.empty()) 46 else if (!CPU.empty()) 47 TargetName = CPU;
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430Subtarget.cpp | 27 const std::string &CPU, 29 MSP430GenSubtargetInfo(TT, CPU, FS) { 26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | MSP430Subtarget.h | 33 MSP430Subtarget(const std::string &TT, const std::string &CPU, 38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | MSP430TargetMachine.cpp | 29 StringRef CPU, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 22 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented 25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { argument 27 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 30 InitCPUSchedModel(CPU); 34 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) { argument 35 if (!CPU.empty()) 36 CPUSchedModel = getSchedModelForCPU(CPU); 42 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument 67 InitMCProcessorInfo(CPU, FS); 88 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) cons [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcSubtarget.cpp | 27 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument 29 SparcGenSubtargetInfo(TT, CPU, FS), 38 std::string CPUName = CPU;
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H A D | SparcTargetMachine.cpp | 29 StringRef CPU, StringRef FS, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS, is64bit), 86 StringRef TT, StringRef CPU, 92 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 98 StringRef TT, StringRef CPU, 104 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | SparcSubtarget.h | 36 SparcSubtarget(const std::string &TT, const std::string &CPU, 47 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZSubtarget.cpp | 25 const std::string &CPU, 27 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), 30 std::string CPUName = CPU; 24 SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | SystemZSubtarget.h | 40 SystemZSubtarget(const std::string &TT, const std::string &CPU, 47 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | SystemZTargetMachine.cpp | 23 StringRef CPU, StringRef FS, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 29 Subtarget(TT, CPU, FS), 22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options, 29 : TargetMachine(T, TT, CPU, FS, Options) {} 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.h | 46 StringRef TT, StringRef CPU); 48 StringRef TT, StringRef CPU); 50 StringRef TT, StringRef CPU); 52 StringRef TT, StringRef CPU);
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/freebsd-9.3-release/contrib/llvm/lib/Target/R600/ |
H A D | AMDGPUSubtarget.cpp | 24 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument 25 AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) { 26 InstrItins = getInstrItineraryForCPU(CPU); 29 StringRef GPU = CPU;
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/freebsd-9.3-release/contrib/llvm/include/llvm/MC/ |
H A D | MCSubtargetInfo.h | 46 uint64_t FeatureBits; // Feature bits for current CPU + FS 49 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, 71 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with 73 void InitMCProcessorInfo(StringRef CPU, StringRef FS); 75 /// InitCPUSchedModel - Recompute scheduling model based on CPU. 76 void InitCPUSchedModel(StringRef CPU); 86 /// getSchedModelForCPU - Get the machine model of a CPU. 88 const MCSchedModel *getSchedModelForCPU(StringRef CPU) const; 90 /// getSchedModel - Get the machine model for this subtarget's CPU. 132 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 70 StringRef CPU; member in class:__anon2522::X86AsmBackend 74 : MCAsmBackend(), CPU(_CPU) { 75 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && 76 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && 77 CPU != "i686" && CPU ! 349 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU) argument 362 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) argument 372 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) argument 384 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) argument 710 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, bool Is64Bit) argument 724 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, bool SupportsCU) argument 745 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, bool SupportsCU, MachO::CPUSubTypeX86 st) argument 800 createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument 818 createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument [all...] |
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.h | 34 MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU, 48 StringRef TT, StringRef CPU);
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/freebsd-9.3-release/contrib/llvm/tools/clang/include/clang/Basic/ |
H A D | TargetOptions.h | 32 /// If given, the name of the target CPU to generate code for. 33 std::string CPU; member in class:clang::TargetOptions
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.h | 39 std::string ParseARMTriple(StringRef TT, StringRef CPU); 44 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 60 StringRef TT, StringRef CPU);
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 49 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument 50 HexagonGenSubtargetInfo(TT, CPU, FS), 51 CPUString(CPU.str()) { 72 // Initialize scheduling itinerary for the specified CPU.
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