1224133Sdim//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file describes the subtarget options of a Target machine. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14224133Sdim#ifndef LLVM_MC_MCSUBTARGET_H 15224133Sdim#define LLVM_MC_MCSUBTARGET_H 16224133Sdim 17252723Sdim#include "llvm/MC/MCInstrItineraries.h" 18224133Sdim#include "llvm/MC/SubtargetFeature.h" 19224133Sdim#include <string> 20224133Sdim 21224133Sdimnamespace llvm { 22224133Sdim 23224133Sdimclass StringRef; 24224133Sdim 25224133Sdim//===----------------------------------------------------------------------===// 26224133Sdim/// 27224133Sdim/// MCSubtargetInfo - Generic base class for all target subtargets. 28224133Sdim/// 29224133Sdimclass MCSubtargetInfo { 30224133Sdim std::string TargetTriple; // Target triple 31224133Sdim const SubtargetFeatureKV *ProcFeatures; // Processor feature list 32224133Sdim const SubtargetFeatureKV *ProcDesc; // Processor descriptions 33245431Sdim 34245431Sdim // Scheduler machine model 35245431Sdim const SubtargetInfoKV *ProcSchedModels; 36245431Sdim const MCWriteProcResEntry *WriteProcResTable; 37245431Sdim const MCWriteLatencyEntry *WriteLatencyTable; 38245431Sdim const MCReadAdvanceEntry *ReadAdvanceTable; 39245431Sdim const MCSchedModel *CPUSchedModel; 40245431Sdim 41245431Sdim const InstrStage *Stages; // Instruction itinerary stages 42245431Sdim const unsigned *OperandCycles; // Itinerary operand cycles 43245431Sdim const unsigned *ForwardingPaths; // Forwarding paths 44224133Sdim unsigned NumFeatures; // Number of processor features 45224133Sdim unsigned NumProcs; // Number of processors 46224133Sdim uint64_t FeatureBits; // Feature bits for current CPU + FS 47224133Sdim 48224133Sdimpublic: 49224133Sdim void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, 50224133Sdim const SubtargetFeatureKV *PF, 51224133Sdim const SubtargetFeatureKV *PD, 52245431Sdim const SubtargetInfoKV *ProcSched, 53245431Sdim const MCWriteProcResEntry *WPR, 54245431Sdim const MCWriteLatencyEntry *WL, 55245431Sdim const MCReadAdvanceEntry *RA, 56245431Sdim const InstrStage *IS, 57224133Sdim const unsigned *OC, const unsigned *FP, 58224133Sdim unsigned NF, unsigned NP); 59224133Sdim 60224133Sdim /// getTargetTriple - Return the target triple string. 61224133Sdim StringRef getTargetTriple() const { 62224133Sdim return TargetTriple; 63224133Sdim } 64224133Sdim 65224133Sdim /// getFeatureBits - Return the feature bits. 66224133Sdim /// 67224133Sdim uint64_t getFeatureBits() const { 68224133Sdim return FeatureBits; 69224133Sdim } 70224133Sdim 71245431Sdim /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with 72245431Sdim /// feature string). Recompute feature bits and scheduling model. 73245431Sdim void InitMCProcessorInfo(StringRef CPU, StringRef FS); 74224133Sdim 75263509Sdim /// InitCPUSchedModel - Recompute scheduling model based on CPU. 76263509Sdim void InitCPUSchedModel(StringRef CPU); 77263509Sdim 78224133Sdim /// ToggleFeature - Toggle a feature and returns the re-computed feature 79224133Sdim /// bits. This version does not change the implied bits. 80224133Sdim uint64_t ToggleFeature(uint64_t FB); 81224133Sdim 82224133Sdim /// ToggleFeature - Toggle a feature and returns the re-computed feature 83224133Sdim /// bits. This version will also change all implied bits. 84224133Sdim uint64_t ToggleFeature(StringRef FS); 85224133Sdim 86245431Sdim /// getSchedModelForCPU - Get the machine model of a CPU. 87245431Sdim /// 88245431Sdim const MCSchedModel *getSchedModelForCPU(StringRef CPU) const; 89245431Sdim 90245431Sdim /// getSchedModel - Get the machine model for this subtarget's CPU. 91245431Sdim /// 92245431Sdim const MCSchedModel *getSchedModel() const { return CPUSchedModel; } 93245431Sdim 94245431Sdim /// Return an iterator at the first process resource consumed by the given 95245431Sdim /// scheduling class. 96245431Sdim const MCWriteProcResEntry *getWriteProcResBegin( 97245431Sdim const MCSchedClassDesc *SC) const { 98245431Sdim return &WriteProcResTable[SC->WriteProcResIdx]; 99245431Sdim } 100245431Sdim const MCWriteProcResEntry *getWriteProcResEnd( 101245431Sdim const MCSchedClassDesc *SC) const { 102245431Sdim return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries; 103245431Sdim } 104245431Sdim 105245431Sdim const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, 106245431Sdim unsigned DefIdx) const { 107245431Sdim assert(DefIdx < SC->NumWriteLatencyEntries && 108245431Sdim "MachineModel does not specify a WriteResource for DefIdx"); 109245431Sdim 110245431Sdim return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; 111245431Sdim } 112245431Sdim 113245431Sdim int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, 114245431Sdim unsigned WriteResID) const { 115245431Sdim // TODO: The number of read advance entries in a class can be significant 116245431Sdim // (~50). Consider compressing the WriteID into a dense ID of those that are 117245431Sdim // used by ReadAdvance and representing them as a bitset. 118245431Sdim for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx], 119245431Sdim *E = I + SC->NumReadAdvanceEntries; I != E; ++I) { 120245431Sdim if (I->UseIdx < UseIdx) 121245431Sdim continue; 122245431Sdim if (I->UseIdx > UseIdx) 123245431Sdim break; 124245431Sdim // Find the first WriteResIdx match, which has the highest cycle count. 125245431Sdim if (!I->WriteResourceID || I->WriteResourceID == WriteResID) { 126245431Sdim return I->Cycles; 127245431Sdim } 128245431Sdim } 129245431Sdim return 0; 130245431Sdim } 131245431Sdim 132224133Sdim /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU. 133224133Sdim /// 134224133Sdim InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const; 135245431Sdim 136245431Sdim /// Initialize an InstrItineraryData instance. 137245431Sdim void initInstrItins(InstrItineraryData &InstrItins) const; 138224133Sdim}; 139224133Sdim 140224133Sdim} // End llvm namespace 141224133Sdim 142224133Sdim#endif 143