Searched refs:v4i8 (Results 1 - 20 of 20) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1015 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw
1020 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus
1026 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw
1032 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw
1392 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, member in class:MVT
1405 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, member in class:MVT
1419 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm member in class:MVT
1453 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd
1482 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 },
1483 { ISD::ZERO_EXTEND, MVT::v4i8, MV
1567 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, member in class:MVT
1578 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, member in class:MVT
1589 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb member in class:MVT
[all...]
H A DX86ISelLowering.cpp877 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
886 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
973 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1027 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1114 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1329 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1844 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1853 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp213 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
214 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0},
251 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0},
334 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
335 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
367 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
368 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
382 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
383 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
480 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8,
[all...]
H A DARMISelLowering.cpp400 // It is legal to extload from v4i8 to v4i16 or v4i32.
403 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
414 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
420 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
957 // It is legal to extload from v4i8 to v4i16 or v4i32.
958 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
8747 case MVT::v4i8:
16149 if ((Ty == MVT::v4i8 || T
[all...]
H A DARMISelDAGToDAG.cpp1787 } else if (LoadedVT == MVT::v4i8 &&
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h75 v4i8 = 28, // 4 x i8
356 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
477 case v4i8:
680 case v4i8:
797 case v4i8:
1033 if (NumElements == 4) return MVT::v4i8;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp618 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
1016 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1074 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1452 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1498 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1656 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1657 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1658 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1665 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1686 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MV
[all...]
H A DHexagonISelDAGToDAG.cpp98 case MVT::v4i8:
488 case MVT::v4i8:
H A DHexagonISelLoweringHVX.cpp1106 DAG.getSplatBuildVector(MVT::v4i8, dl, DAG.getConstant(1, dl, MVT::i32));
H A DHexagonInstrInfo.cpp2682 case MVT::v4i8:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp353 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
355 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
395 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
397 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
H A DAArch64ISelLowering.cpp800 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
801 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
914 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
2947 case MVT::v4i8:
3318 // Custom lower trunc store for v4i8 vectors, since it is promoted to v4i16.
3323 assert(MemVT == MVT::v4i8 && VT == MVT::v4i16);
3328 // the word lane which represent the v4i8 subvector. It optimizes the store
3352 // from vector v4i16 to v4i8 or volatile stores of i128.
12127 // %lo = v4i32 sext v4i8 %losrc
12128 // %hi = v4i32 sext v4i8
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp86 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
875 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
932 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
944 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
971 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
984 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp223 case MVT::v4i8:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp93 case MVT::v4i8: return "MVT::v4i8";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp125 case MVT::v4i8:
2292 case MVT::v4i8:
4490 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4780 case MVT::v4i8:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp116 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
H A DSIISelLowering.cpp214 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
219 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
224 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Expand);
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
398 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
402 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
765 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
8517 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
H A DAMDGPUISelLowering.cpp160 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
161 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
162 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp758 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
941 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
945 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1074 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);

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