Lines Matching refs:v4i8
618 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
1016 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1074 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1452 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1498 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1656 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1657 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1658 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1665 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1686 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1692 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1706 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1708 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1737 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
2357 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2392 return DAG.getBitcast(MVT::v4i8, R);