Searched refs:isPredicated (Results 1 - 25 of 36) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
213 CantAnalyze = !isPredicated(*I);
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp368 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
570 if (!HII->isPredicated(MI))
701 if (HII->isPredicated(PacketMI)) {
702 if (!HII->isPredicated(MI))
926 if (!HII->isPredicated(*I))
953 assert(QII->isPredicated(MI) && "Must be predicated instruction");
1207 if (HII->isPredicated(I) || HII->isPredicated(J))
1247 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1468 if (HII->isPredicated(
[all...]
H A DHexagonExpandCondsets.cpp343 if (HII->isPredicated(*DefI))
421 if (HII->isPredicated(*DefI))
491 if (!HII->isPredicated(*DefI))
723 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
758 if (PredValid && HII->isPredicated(*MI)) {
916 if (!HII->isPredicated(*MI))
989 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
H A DHexagonInstrInfo.h223 bool isPredicated(const MachineInstr &MI) const override;
388 bool isPredicated(unsigned Opcode) const;
H A DHexagonPeephole.cpp238 if (QII->isPredicated(MI)) {
H A DHexagonInstrInfo.cpp611 if (Term != MBB.end() && isPredicated(*Term) &&
1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:HexagonInstrInfo
2162 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2446 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2469 assert(isPredicated(MI));
2475 assert(isPredicated(Opcode));
2493 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { function in class:HexagonInstrInfo
3174 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3239 if (isPredicated(MI)) {
3764 if (isPredicated(NewO
[all...]
H A DHexagonNewValueJump.cpp124 if (QII->isPredicated(*II))
H A DHexagonConstExtenders.cpp1698 if (HII->isPredicated(MI))
1825 if (HII->isPredicated(MI))
1943 assert(HII->isPredicated(MI));
H A DHexagonOptAddrMode.cpp129 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp180 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
255 if (!TII->isPredicated(MI)) {
611 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
H A DIfConversion.cpp1110 bool isPredicated = TII->isPredicated(MI); local
1122 if (!isPredicated) {
1137 if (BBI.ClobbersPred && !isPredicated) {
1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T);
1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T);
2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI))
2142 if (I.isDebugInstr() || TII->isPredicated(I))
2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromT
[all...]
H A DTargetSchedule.cpp306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
H A DAggressiveAntiDepBreaker.cpp384 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
462 TII->isPredicated(MI) || MI.isInlineAsm();
H A DBranchFolding.cpp1866 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
1934 if (TII->isPredicated(*TIB))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
327 bool isPredicated() const;
H A DHexagonMCChecker.cpp68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
435 if (std::get<2>(Producer).isPredicated() &&
436 (!Consumer.isPredicated() ||
H A DHexagonMCInstrInfo.cpp35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { function in class:HexagonMCInstrInfo::PredicateInfo
718 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, function in class:HexagonMCInstrInfo
927 if (!isPredicated(MCII, MCI))
H A DHexagonMCCodeEmitter.cpp759 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
763 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h180 bool isPredicated(const MachineInstr &MI) const override;
H A DR600Packetizer.cpp84 if (TII->isPredicated(*BI))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp1033 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) {
1135 if ((isPredicated(BlockA) || isPredicated(BlockB)) &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp327 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
359 CantAnalyze = !isPredicated(*I);
367 if (!isPredicated(*I) &&
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:ARMBaseInstrInfo
2950 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2959 isPredicated(*PotentialAND))
3078 if (isPredicated(*MI))
3207 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3225 if (isPredicated(MI))
4901 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(M
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h876 bool isPredicated(BasicBlock *BB) const { function in class:llvm::InterleavedAccessInfo
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h471 bool isPredicated(const MachineInstr &MI) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1314 virtual bool isPredicated(const MachineInstr &MI) const { return false; } function in class:llvm::TargetInstrInfo

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