/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCInstrInfo.cpp | 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { 213 CantAnalyze = !isPredicated(*I); 221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 368 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; 570 if (!HII->isPredicated(MI)) 701 if (HII->isPredicated(PacketMI)) { 702 if (!HII->isPredicated(MI)) 926 if (!HII->isPredicated(*I)) 953 assert(QII->isPredicated(MI) && "Must be predicated instruction"); 1207 if (HII->isPredicated(I) || HII->isPredicated(J)) 1247 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) 1468 if (HII->isPredicated( [all...] |
H A D | HexagonExpandCondsets.cpp | 343 if (HII->isPredicated(*DefI)) 421 if (HII->isPredicated(*DefI)) 491 if (!HII->isPredicated(*DefI)) 723 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) 758 if (PredValid && HII->isPredicated(*MI)) { 916 if (!HII->isPredicated(*MI)) 989 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
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H A D | HexagonInstrInfo.h | 223 bool isPredicated(const MachineInstr &MI) const override; 388 bool isPredicated(unsigned Opcode) const;
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H A D | HexagonPeephole.cpp | 238 if (QII->isPredicated(MI)) {
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H A D | HexagonInstrInfo.cpp | 611 if (Term != MBB.end() && isPredicated(*Term) && 1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:HexagonInstrInfo 2162 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) 2446 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); 2469 assert(isPredicated(MI)); 2475 assert(isPredicated(Opcode)); 2493 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { function in class:HexagonInstrInfo 3174 if (Cond.empty() || !isPredicated(Cond[0].getImm())) 3239 if (isPredicated(MI)) { 3764 if (isPredicated(NewO [all...] |
H A D | HexagonNewValueJump.cpp | 124 if (QII->isPredicated(*II))
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H A D | HexagonConstExtenders.cpp | 1698 if (HII->isPredicated(MI)) 1825 if (HII->isPredicated(MI)) 1943 assert(HII->isPredicated(MI));
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H A D | HexagonOptAddrMode.cpp | 129 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | CriticalAntiDepBreaker.cpp | 180 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); 255 if (!TII->isPredicated(MI)) { 611 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
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H A D | IfConversion.cpp | 1110 bool isPredicated = TII->isPredicated(MI); local 1122 if (!isPredicated) { 1137 if (BBI.ClobbersPred && !isPredicated) { 1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); 1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); 2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) 2142 if (I.isDebugInstr() || TII->isPredicated(I)) 2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { 2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromT [all...] |
H A D | TargetSchedule.cpp | 306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
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H A D | AggressiveAntiDepBreaker.cpp | 384 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || 462 TII->isPredicated(MI) || MI.isInlineAsm();
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H A D | BranchFolding.cpp | 1866 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI)) 1934 if (TII->isPredicated(*TIB))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.h | 275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI); 327 bool isPredicated() const;
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H A D | HexagonMCChecker.cpp | 68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { 435 if (std::get<2>(Producer).isPredicated() && 436 (!Consumer.isPredicated() ||
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H A D | HexagonMCInstrInfo.cpp | 35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { function in class:HexagonMCInstrInfo::PredicateInfo 718 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, function in class:HexagonMCInstrInfo 927 if (!isPredicated(MCII, MCI))
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H A D | HexagonMCCodeEmitter.cpp | 759 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { 763 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 180 bool isPredicated(const MachineInstr &MI) const override;
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H A D | R600Packetizer.cpp | 84 if (TII->isPredicated(*BI))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | VectorUtils.cpp | 1033 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { 1135 if ((isPredicated(BlockA) || isPredicated(BlockB)) &&
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 327 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { 359 CantAnalyze = !isPredicated(*I); 367 if (!isPredicated(*I) && 483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { function in class:ARMBaseInstrInfo 2950 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) { 2959 isPredicated(*PotentialAND)) 3078 if (isPredicated(*MI)) 3207 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction"); 3225 if (isPredicated(MI)) 4901 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(M [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | VectorUtils.h | 876 bool isPredicated(BasicBlock *BB) const { function in class:llvm::InterleavedAccessInfo
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 471 bool isPredicated(const MachineInstr &MI) const override;
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1314 virtual bool isPredicated(const MachineInstr &MI) const { return false; } function in class:llvm::TargetInstrInfo
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