1//===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Utility functions for Hexagon specific MCInst queries 10// 11//===----------------------------------------------------------------------===// 12 13#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H 14#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H 15 16#include "llvm/ADT/SmallVector.h" 17#include "llvm/ADT/StringRef.h" 18#include "llvm/ADT/iterator_range.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/Support/MathExtras.h" 21#include <cstddef> 22#include <cstdint> 23 24namespace llvm { 25 26class HexagonMCChecker; 27class MCContext; 28class MCExpr; 29class MCInstrDesc; 30class MCInstrInfo; 31class MCRegisterInfo; 32class MCSubtargetInfo; 33 34class DuplexCandidate { 35public: 36 unsigned packetIndexI, packetIndexJ, iClass; 37 38 DuplexCandidate(unsigned i, unsigned j, unsigned iClass) 39 : packetIndexI(i), packetIndexJ(j), iClass(iClass) {} 40}; 41 42namespace Hexagon { 43 44class PacketIterator { 45 MCInstrInfo const &MCII; 46 MCInst::const_iterator BundleCurrent; 47 MCInst::const_iterator BundleEnd; 48 MCInst::const_iterator DuplexCurrent; 49 MCInst::const_iterator DuplexEnd; 50 51public: 52 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst); 53 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t); 54 55 PacketIterator &operator++(); 56 MCInst const &operator*() const; 57 bool operator==(PacketIterator const &Other) const; 58 bool operator!=(PacketIterator const &Other) const { 59 return !(*this == Other); 60 } 61}; 62 63} // end namespace Hexagon 64 65namespace HexagonMCInstrInfo { 66 67size_t const innerLoopOffset = 0; 68int64_t const innerLoopMask = 1 << innerLoopOffset; 69 70size_t const outerLoopOffset = 1; 71int64_t const outerLoopMask = 1 << outerLoopOffset; 72 73// do not reorder memory load/stores by default load/stores are re-ordered 74// and by default loads can be re-ordered 75size_t const memReorderDisabledOffset = 2; 76int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset; 77 78size_t const bundleInstructionsOffset = 1; 79 80void addConstant(MCInst &MI, uint64_t Value, MCContext &Context); 81void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, 82 MCInst const &MCI); 83 84// Returns a iterator range of instructions in this bundle 85iterator_range<Hexagon::PacketIterator> 86bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI); 87iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI); 88 89// Returns the number of instructions in the bundle 90size_t bundleSize(MCInst const &MCI); 91 92// Put the packet in to canonical form, compound, duplex, pad, and shuffle 93bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 94 MCContext &Context, MCInst &MCB, 95 HexagonMCChecker *Checker, 96 bool AttemptCompatibility = false); 97 98// Create a duplex instruction given the two subinsts 99MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, 100 MCInst const &inst1); 101MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, 102 MCOperand const &MO); 103 104// Convert this instruction in to a duplex subinst 105MCInst deriveSubInst(MCInst const &Inst); 106 107// Return the extender for instruction at Index or nullptr if none 108MCInst const *extenderForIndex(MCInst const &MCB, size_t Index); 109void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, 110 MCInst const &MCI); 111 112// Return memory access size in bytes 113unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI); 114 115// Return memory access size 116unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI); 117 118MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); 119 120// Return which duplex group this instruction belongs to 121unsigned getDuplexCandidateGroup(MCInst const &MI); 122 123// Return a list of all possible instruction duplex combinations 124SmallVector<DuplexCandidate, 8> 125getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 126 MCInst const &MCB); 127unsigned getDuplexRegisterNumbering(unsigned Reg); 128 129MCExpr const &getExpr(MCExpr const &Expr); 130 131// Return the index of the extendable operand 132unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI); 133 134// Return a reference to the extendable operand 135MCOperand const &getExtendableOperand(MCInstrInfo const &MCII, 136 MCInst const &MCI); 137 138// Return the implicit alignment of the extendable operand 139unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI); 140 141// Return the number of logical bits of the extendable operand 142unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI); 143 144// Check if the extendable operand is signed. 145bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI); 146 147// Return the max value that a constant extendable operand can have 148// without being extended. 149int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI); 150 151// Return the min value that a constant extendable operand can have 152// without being extended. 153int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI); 154 155// Return instruction name 156StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI); 157 158// Return the operand index for the new value. 159unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI); 160 161// Return the operand that consumes or produces a new value. 162MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI); 163unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI); 164MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII, 165 MCInst const &MCI); 166 167// Return the Hexagon ISA class for the insn. 168unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI); 169 170/// Return the resources used by this instruction 171unsigned getCVIResources(MCInstrInfo const &MCII, 172 MCSubtargetInfo const &STI, 173 MCInst const &MCI); 174 175/// Return the slots used by the insn. 176unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 177 MCInst const &MCI); 178unsigned getOtherReservedSlots(MCInstrInfo const &MCII, 179 MCSubtargetInfo const &STI, MCInst const &MCI); 180bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI); 181 182// Does the packet have an extender for the instruction at Index 183bool hasExtenderForIndex(MCInst const &MCB, size_t Index); 184 185bool hasImmExt(MCInst const &MCI); 186 187// Return whether the instruction is a legal new-value producer. 188bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI); 189bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI); 190bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI); 191unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb); 192 193int64_t minConstant(MCInst const &MCI, size_t Index); 194template <unsigned N, unsigned S> 195bool inRange(MCInst const &MCI, size_t Index) { 196 return isShiftedUInt<N, S>(minConstant(MCI, Index)); 197} 198template <unsigned N, unsigned S> 199bool inSRange(MCInst const &MCI, size_t Index) { 200 return isShiftedInt<N, S>(minConstant(MCI, Index)); 201} 202template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) { 203 return isUInt<N>(minConstant(MCI, Index)); 204} 205 206// Return the instruction at Index 207MCInst const &instruction(MCInst const &MCB, size_t Index); 208bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI); 209 210// Returns whether this MCInst is a wellformed bundle 211bool isBundle(MCInst const &MCI); 212 213// Return whether the insn is an actual insn. 214bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI); 215bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI); 216bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI); 217bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI); 218bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI); 219 220// Return whether the instruction needs to be constant extended. 221bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI); 222bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI); 223 224// Is this double register suitable for use in a duplex subinst 225bool isDblRegForSubInst(unsigned Reg); 226 227// Is this a duplex instruction 228bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI); 229 230// Can these instructions be duplexed 231bool isDuplexPair(MCInst const &MIa, MCInst const &MIb); 232 233// Can these duplex classes be combine in to a duplex instruction 234bool isDuplexPairMatch(unsigned Ga, unsigned Gb); 235 236// Return true if the insn may be extended based on the operand value. 237bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI); 238 239// Return whether the instruction must be always extended. 240bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI); 241 242/// Return whether it is a floating-point insn. 243bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI); 244 245bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI); 246 247// Returns whether this instruction is an immediate extender 248bool isImmext(MCInst const &MCI); 249 250// Returns whether this bundle is an endloop0 251bool isInnerLoop(MCInst const &MCI); 252 253// Is this an integer register 254bool isIntReg(unsigned Reg); 255 256// Is this register suitable for use in a duplex subinst 257bool isIntRegForSubInst(unsigned Reg); 258bool isMemReorderDisabled(MCInst const &MCI); 259 260// Return whether the insn is a new-value consumer. 261bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); 262/// Return true if the operand is a new-value store insn. 263bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI); 264bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short); 265 266// Can these two instructions be duplexed 267bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, 268 bool ExtendedA, MCInst const &MIb, bool ExtendedB, 269 bool bisReversable, MCSubtargetInfo const &STI); 270 271// Returns whether this bundle is an endloop1 272bool isOuterLoop(MCInst const &MCI); 273 274// Return whether this instruction is predicated 275bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI); 276bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI); 277bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI); 278 279// Return whether the predicate sense is true 280bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI); 281 282// Return true if this is a scalar predicate register. 283bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg); 284 285// Returns true if the Ith operand is a predicate register. 286bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I); 287 288// Return whether the insn is a prefix. 289bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI); 290 291// Return whether the insn is solo, i.e., cannot be in a packet. 292bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI); 293 294/// Return whether the insn can be packaged only with A and X-type insns. 295bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI); 296 297/// Return whether the insn can be packaged only with an A-type insn in slot #1. 298bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI); 299bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI); 300bool isSubInstruction(MCInst const &MCI); 301bool isVector(MCInstrInfo const &MCII, MCInst const &MCI); 302bool mustExtend(MCExpr const &Expr); 303bool mustNotExtend(MCExpr const &Expr); 304 305// Returns true if this instruction requires a slot to execute. 306bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI); 307 308unsigned packetSize(StringRef CPU); 309 310// Returns the maximum number of slots available in the given 311// subtarget's packets. 312unsigned packetSizeSlots(MCSubtargetInfo const &STI); 313 314// Returns the number of slots consumed by this packet, considering duplexed 315// and compound instructions. 316unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 317 MCInst const &MCI); 318 319 320// Pad the bundle with nops to satisfy endloop requirements 321void padEndloop(MCInst &MCI, MCContext &Context); 322class PredicateInfo { 323public: 324 PredicateInfo() : Register(0), Operand(0), PredicatedTrue(false) {} 325 PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue) 326 : Register(Register), Operand(Operand), PredicatedTrue(PredicatedTrue) {} 327 bool isPredicated() const; 328 unsigned Register; 329 unsigned Operand; 330 bool PredicatedTrue; 331}; 332PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI); 333bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI); 334 335// Replace the instructions inside MCB, represented by Candidate 336void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate); 337 338bool s27_2_reloc(MCExpr const &Expr); 339// Marks a bundle as endloop0 340void setInnerLoop(MCInst &MCI); 341void setMemReorderDisabled(MCInst &MCI); 342void setMustExtend(MCExpr const &Expr, bool Val = true); 343void setMustNotExtend(MCExpr const &Expr, bool Val = true); 344void setS27_2_reloc(MCExpr const &Expr, bool Val = true); 345 346// Marks a bundle as endloop1 347void setOuterLoop(MCInst &MCI); 348 349// Would duplexing this instruction create a requirement to extend 350bool subInstWouldBeExtended(MCInst const &potentialDuplex); 351unsigned SubregisterBit(unsigned Consumer, unsigned Producer, 352 unsigned Producer2); 353 354bool IsVecRegSingle(unsigned VecReg); 355bool IsVecRegPair(unsigned VecReg); 356bool IsReverseVecRegPair(unsigned VecReg); 357bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer); 358 359/// Returns an ordered pair of the constituent register ordinals for 360/// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1") 361/// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }. 362std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair); 363 364// Attempt to find and replace compound pairs 365void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 366 MCContext &Context, MCInst &MCI); 367 368} // end namespace HexagonMCInstrInfo 369 370} // end namespace llvm 371 372#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H 373