| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineScheduler.cpp | 373 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass);
376 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass);
379 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass);
382 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass);
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| H A D | SILowerI1Copies.cpp | 492 MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, function
85 MachineRegisterInfo::constrainRegClass(Register Reg, function in class:MachineRegisterInfo
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
109 if (!::constrainRegClass(
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| H A D | OptimizePHIs.cpp | 181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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| H A D | MachineLoopUtils.cpp | 67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
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| H A D | UnreachableBlockElim.cpp | 185 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
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| H A D | TargetInstrInfo.cpp | 824 MRI.constrainRegClass(RegA, RC);
826 MRI.constrainRegClass(RegB, RC);
828 MRI.constrainRegClass(RegX, RC);
830 MRI.constrainRegClass(RegY, RC);
832 MRI.constrainRegClass(RegC, RC);
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| H A D | TailDuplicator.cpp | 250 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
427 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC);
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| H A D | ModuloSchedule.cpp | 1190 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
1237 MRI.constrainRegClass(MI.getOperand(1).getReg(),
1486 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue()));
1496 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg));
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| H A D | TwoAddressInstructionPass.cpp | 1336 MRI->constrainRegClass(DstReg, RC);
1449 MRI->constrainRegClass(RegA, RC);
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| H A D | MachineBasicBlock.cpp | 548 if (!MRI.constrainRegClass(VirtReg, RC))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionalCompares.cpp | 643 MRI->constrainRegClass(HeadCond[2].getReg(),
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
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| H A D | AArch64InstrInfo.cpp | 615 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
621 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
661 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
665 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
669 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
672 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
700 MRI.constrainRegClass(TrueReg, RC);
701 MRI.constrainRegClass(FalseReg, RC);
1120 !MRI->constrainRegClass(Reg, OpRegCstraints))
3070 MF.getRegInfo().constrainRegClass(SrcRe
[all...] |
| H A D | AArch64RegisterInfo.cpp | 539 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 237 if (!MRI.constrainRegClass(KilledProdReg,
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| H A D | PPCRegisterInfo.cpp | 1313 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1339 MRI.constrainRegClass(BaseReg,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 164 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
205 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
668 if (!MRI->constrainRegClass(FrameReg, RegClass))
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| H A D | A15SDOptimizer.cpp | 641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
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| H A D | ARMBaseRegisterInfo.cpp | 654 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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| H A D | ARMLoadStoreOptimizer.cpp | 2367 MRI->constrainRegClass(FirstReg, TRC);
2368 MRI->constrainRegClass(SecondReg, TRC);
2560 MRI.constrainRegClass(NewReg, TRC);
2563 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 323 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
453 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
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| H A D | FastISel.cpp | 2084 if (!MRI.constrainRegClass(Op, RegClass)) {
2292 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 580 /// constrainRegClass(ToReg, getRegClass(FromReg))
680 /// constrainRegClass - Constrain the register class of the specified virtual
691 const TargetRegisterClass *constrainRegClass(Register Reg,
703 /// \note Use this method instead of constrainRegClass and
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 509 if (!MRI.constrainRegClass(DestReg, PreviousClass))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.cpp | 135 // If the register already has a class, fallback to MRI::constrainRegClass.
138 return MRI.constrainRegClass(Reg, &RC);
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