Searched refs:WR4 (Results 1 - 25 of 77) sorted by relevance

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/freebsd-13-stable/sys/arm/freescale/imx/
H A Dimx6_ccm.c75 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) function
97 WR4(sc, CCM_CCGR0, reg);
102 WR4(sc, CCM_CCGR1, reg);
109 WR4(sc, CCM_CCGR2, reg);
114 WR4(sc, CCM_CCGR3, reg);
119 WR4(sc, CCM_CCGR4, reg);
124 WR4(sc, CCM_CCGR5, reg);
129 WR4(sc, CCM_CCGR6, reg);
181 WR4(sc, CCM_CGPR, reg);
184 WR4(s
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H A Dimx_epit.c142 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value) function
203 WR4(sc, EPIT_LR, 0xffffffff);
204 WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
234 WR4(sc, EPIT_CR, sc->ctlreg);
235 WR4(sc, EPIT_SR, EPIT_SR_OCIF);
247 WR4(sc, EPIT_LR, ticks);
261 WR4(sc, EPIT_CR, sc->ctlreg);
286 WR4(sc, EPIT_CR, sc->ctlreg);
450 WR4(sc, EPIT_CR, 0);
H A Dimx6_snvs.c89 WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value) function
104 WR4(sc, SNVS_LPCR, sc->lpcr);
163 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
164 WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
/freebsd-13-stable/sys/arm/nvidia/drm2/
H A Dtegra_dc.c58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
426 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val);
429 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y));
430 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h));
431 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size));
434 WR4(sc, DC_WIN_DDA_INCREMENT,
436 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda);
437 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda);
440 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]);
442 WR4(s
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H A Dtegra_hdmi.c61 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
357 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
359 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW,
361 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,
363 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW,
365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH,
368 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL,
388 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
390 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW,
392 WR4(s
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/freebsd-13-stable/sys/dev/ffec/
H A Dif_ffec.c233 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) function
326 WR4(sc, FEC_IER_REG, FEC_IER_MII);
328 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
350 WR4(sc, FEC_IER_REG, FEC_IER_MII);
352 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
438 WR4(sc, FEC_RCR_REG, rcr);
439 WR4(sc, FEC_TCR_REG, tcr);
440 WR4(sc, FEC_ECR_REG, ecr);
492 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
493 WR4(s
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/freebsd-13-stable/sys/arm/xilinx/
H A Dzy7_spi.c98 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
168 WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte);
211 WR4(sc, ZY7_SPI_INTR_DIS_REG,
241 WR4(sc, ZY7_SPI_INTR_STAT_REG,
251 WR4(sc, ZY7_SPI_INTR_DIS_REG,
261 WR4(sc, ZY7_SPI_INTR_STAT_REG,
275 WR4(sc, ZY7_SPI_INTR_DIS_REG,
277 WR4(sc, ZY7_SPI_INTR_EN_REG,
289 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow);
321 WR4(s
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H A Duart_dev_cdnc.c59 #define WR4(bas, reg, value) \ macro
211 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
212 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
259 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
272 WR4(bas, CDNC_UART_CTRL_REG,
276 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
277 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
280 WR4(bas, CDNC_UART_MODEM_STAT_REG,
285 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
286 WR4(ba
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H A Dzy7_qspi.c108 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
253 WR4(sc, ZY7_QSPI_TXD1_REG, data);
256 WR4(sc, ZY7_QSPI_TXD2_REG, data);
259 WR4(sc, ZY7_QSPI_TXD3_REG, data);
262 WR4(sc, ZY7_QSPI_TXD0_REG, data);
323 WR4(sc, ZY7_QSPI_INTR_DIS_REG,
353 WR4(sc, ZY7_QSPI_INTR_STAT_REG,
363 WR4(sc, ZY7_QSPI_INTR_DIS_REG,
377 WR4(sc, ZY7_QSPI_INTR_STAT_REG,
392 WR4(s
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H A Dzy7_slcr.c79 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
119 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
127 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
141 WR4(sc, ZY7_SLCR_REBOOT_STAT,
145 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
168 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
171 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
199 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
244 WR4(s
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H A Dzy7_devcfg.c102 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
407 WR4(sc, ZY7_DEVCFG_CTRL,
420 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
436 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
437 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
441 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
450 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
461 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
473 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
474 WR4(s
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H A Dzy7_gpio.c98 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro
207 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
215 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
220 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
222 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
242 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
246 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
278 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
/freebsd-13-stable/sys/arm64/broadcom/genet/
H A Dif_genet.c85 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_MAC], (reg), (val)) macro
449 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
453 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
456 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
459 WR4(sc, GENET_UMAC_CMD, 0);
460 WR4(sc, GENET_UMAC_CMD,
463 WR4(sc, GENET_UMAC_CMD, 0);
465 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
467 WR4(sc, GENET_UMAC_MIB_CTRL, 0);
469 WR4(s
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/freebsd-13-stable/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c327 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
576 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
581 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
585 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
589 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
593 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
604 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
610 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
614 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
618 WR4(s
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H A Dtegra210_pmc.c191 WR4(struct tegra210_pmc_softc *sc, bus_size_t r, uint32_t v) function
246 WR4(sc, PMC_PWRGATE_TOGGLE,
273 WR4(sc, PMC_GPU_RG_CNTRL, 0);
287 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
509 WR4(sc, PMC_SCRATCH0, 0xDEADBEEF);
514 WR4(sc, PMC_SCRATCH0, 0xBADC0DE);
519 WR4(sc, PMC_SCRATCH0, orig);
582 WR4(sc, PMC_CNTRL, reg);
590 WR4(sc, PMC_CNTRL, reg);
595 WR4(s
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H A Dtegra210_clk_pll.c608 WR4(sc, sc->base_reg, reg);
621 WR4(sc, sc->base_reg, reg);
764 WR4(sc, sc->base_reg, reg);
770 WR4(sc, PLLE_AUX, reg);
780 WR4(sc, sc->misc_reg, reg);
785 WR4(sc, PLLE_SS_CNTL, reg);
789 WR4(sc, sc->base_reg, reg);
806 WR4(sc, PLLE_SS_CNTL, reg);
809 WR4(sc, PLLE_SS_CNTL, reg);
813 WR4(s
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/freebsd-13-stable/sys/arm64/qoriq/
H A Dqoriq_therm.c107 WR4(struct qoriq_therm_softc *sc, bus_size_t addr, uint32_t val) function
227 WR4(sc, TMU_TTRCR(i), ranges[i]);
238 WR4(sc, TMU_TTCFGR, calibs[i]);
239 WR4(sc, TMU_TSCFGR, calibs[i + 1]);
315 WR4(sc, TMU_TMR, 0);
319 WR4(sc, TMU_TIER, 0);
323 WR4(sc, TMUV1_TMTMIR, 0x0F);
325 WR4(sc, TMUV2_TMTMIR, 0x0F); /* disable */
327 WR4(sc, TMUV2_TEUMR(0), 0x51009c00);
329 WR4(s
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/freebsd-13-stable/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c245 WR4(struct bcm_sdhost_softc *sc, bus_size_t off, uint32_t val) function
281 WR4(sc, off & ~3, val32);
292 WR4(sc, off & ~3, val32);
348 WR4(sc, HC_POWER, 0);
350 WR4(sc, HC_COMMAND, 0);
351 WR4(sc, HC_ARGUMENT, 0);
352 WR4(sc, HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT);
353 WR4(sc, HC_CLOCKDIVISOR, 0);
354 WR4(sc, HC_HOSTSTATUS, HC_HSTST_RESET);
355 WR4(s
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/freebsd-13-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c422 WR4(sc, sc->base_reg, reg);
435 WR4(sc, sc->base_reg, reg);
572 WR4(sc, sc->base_reg, reg);
577 WR4(sc, PLLE_AUX, reg);
587 WR4(sc, sc->misc_reg, reg);
592 WR4(sc, PLLE_SS_CNTL, reg);
598 WR4(sc, sc->base_reg, reg);
611 WR4(sc, PLLE_SS_CNTL, reg);
614 WR4(sc, PLLE_SS_CNTL, reg);
618 WR4(s
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H A Dtegra124_xusbpadctl.c173 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
378 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
387 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
389 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
394 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
418 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
425 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
430 WR4(s
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/freebsd-13-stable/sys/arm64/rockchip/
H A Drk_tsadc.c90 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
416 WR4(sc, TSADC_INT_EN, val);
420 WR4(sc, TSADC_COMP_SHUT(sensor->channel), val);
423 WR4(sc, TSADC_AUTO_CON, val);
427 WR4(sc, TSADC_COMP_INT(sensor->channel), val);
430 WR4(sc, TSADC_INT_EN, val);
446 WR4(sc, TSADC_AUTO_CON, val);
450 WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */
451 WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */
452 WR4(s
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/freebsd-13-stable/sys/arm/nvidia/
H A Dtegra_rtc.c77 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
156 WR4(sc, RTC_SECONDS, tv.tv_sec);
171 WR4(sc, RTC_INTR_STATUS, status);
231 WR4(sc, RTC_SECONDS_ALARM0, 0);
232 WR4(sc, RTC_SECONDS_ALARM1, 0);
233 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF);
234 WR4(sc, RTC_INTR_MASK, 0);
H A Dtegra_i2c.c193 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
246 WR4(sc, I2C_FIFO_CONTROL, reg);
274 WR4(sc, I2C_CLK_DIVISOR,
285 WR4(sc, I2C_BUS_CLEAR_CONFIG,
290 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
300 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
334 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
335 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
336 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
341 WR4(s
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/freebsd-13-stable/sys/dev/cadence/
H A Dif_cgem.c223 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
285 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
287 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
290 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
291 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
363 WR4(sc, CGEM_HASH_TOP, hashes[0]);
364 WR4(sc, CGEM_HASH_BOT, hashes[1]);
365 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
403 WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr);
404 WR4(s
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/freebsd-13-stable/sys/arm/allwinner/
H A Daw_usb3phy.c109 #define WR4(res, o, v) bus_write_4(res, (o), (v)) macro
131 WR4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL, val);
137 WR4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL, val);
143 WR4(sc->res, USB3PHY_APP, val);
145 WR4(sc->res, USB3PHY_PHY_TUNE_LOW, PTL_MAGIC);
158 WR4(sc->res, USB3PHY_PHY_TUNE_HIGH, val);

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