1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Thomas Skibo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31/*
32 * A GPIO driver for Xilinx Zynq-7000.
33 *
34 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
35 *
36 * Pins 53-0 are sent to the MIO.  Any MIO pins not used by a PS peripheral are
37 * available as a GPIO pin.  Pins 64-127 are sent to the PL (FPGA) section of
38 * Zynq as EMIO signals.
39 *
40 * The hardware provides a way to use IOs as interrupt sources but the
41 * gpio framework doesn't seem to have hooks for this.
42 *
43 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
44 * (v1.4) November 16, 2012.  Xilinx doc UG585.  GPIO is covered in
45 * chater 14.  Register definitions are in appendix B.19.
46 */
47
48#include <sys/cdefs.h>
49__FBSDID("$FreeBSD$");
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/conf.h>
54#include <sys/bus.h>
55#include <sys/kernel.h>
56#include <sys/module.h>
57#include <sys/lock.h>
58#include <sys/mutex.h>
59#include <sys/resource.h>
60#include <sys/rman.h>
61#include <sys/gpio.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65#include <machine/stdarg.h>
66
67#include <dev/gpio/gpiobusvar.h>
68#include <dev/ofw/ofw_bus.h>
69#include <dev/ofw/ofw_bus_subr.h>
70
71#include "gpio_if.h"
72
73#define NUMBANKS	4
74#define MAXPIN		(32*NUMBANKS)
75
76#define MIO_PIN		0	/* pins 0-53 go to MIO */
77#define NUM_MIO_PINS	54
78#define EMIO_PIN	64	/* pins 64-127 go to PL */
79#define NUM_EMIO_PINS	64
80
81#define VALID_PIN(u)	(((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \
82			 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS))
83
84#define ZGPIO_LOCK(sc)			mtx_lock(&(sc)->sc_mtx)
85#define	ZGPIO_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
86#define ZGPIO_LOCK_INIT(sc) \
87	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev),	\
88	    "gpio", MTX_DEF)
89#define ZGPIO_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx);
90
91struct zy7_gpio_softc {
92	device_t	dev;
93	device_t	busdev;
94	struct mtx	sc_mtx;
95	struct resource *mem_res;	/* Memory resource */
96};
97
98#define WR4(sc, off, val)	bus_write_4((sc)->mem_res, (off), (val))
99#define RD4(sc, off)		bus_read_4((sc)->mem_res, (off))
100
101/* Xilinx Zynq-7000 GPIO register definitions:
102 */
103#define ZY7_GPIO_MASK_DATA_LSW(b)	(0x0000+8*(b))	/* maskable wr lo */
104#define ZY7_GPIO_MASK_DATA_MSW(b)	(0x0004+8*(b))	/* maskable wr hi */
105#define ZY7_GPIO_DATA(b)		(0x0040+4*(b))	/* in/out data */
106#define ZY7_GPIO_DATA_RO(b)		(0x0060+4*(b))	/* input data */
107
108#define ZY7_GPIO_DIRM(b)		(0x0204+0x40*(b)) /* direction mode */
109#define ZY7_GPIO_OEN(b)			(0x0208+0x40*(b)) /* output enable */
110#define ZY7_GPIO_INT_MASK(b)		(0x020c+0x40*(b)) /* int mask */
111#define ZY7_GPIO_INT_EN(b)		(0x0210+0x40*(b)) /* int enable */
112#define ZY7_GPIO_INT_DIS(b)		(0x0214+0x40*(b)) /* int disable */
113#define ZY7_GPIO_INT_STAT(b)		(0x0218+0x40*(b)) /* int status */
114#define ZY7_GPIO_INT_TYPE(b)		(0x021c+0x40*(b)) /* int type */
115#define ZY7_GPIO_INT_POLARITY(b)	(0x0220+0x40*(b)) /* int polarity */
116#define ZY7_GPIO_INT_ANY(b)		(0x0224+0x40*(b)) /* any edge */
117
118static device_t
119zy7_gpio_get_bus(device_t dev)
120{
121	struct zy7_gpio_softc *sc;
122
123	sc = device_get_softc(dev);
124
125	return (sc->busdev);
126}
127
128static int
129zy7_gpio_pin_max(device_t dev, int *maxpin)
130{
131
132	*maxpin = MAXPIN;
133	return (0);
134}
135
136/* Get a specific pin's capabilities. */
137static int
138zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
139{
140
141	if (!VALID_PIN(pin))
142		return (EINVAL);
143
144	*caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
145
146	return (0);
147}
148
149/* Get a specific pin's name. */
150static int
151zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
152{
153
154	if (!VALID_PIN(pin))
155		return (EINVAL);
156
157	if (pin < NUM_MIO_PINS) {
158		snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
159		name[GPIOMAXNAME - 1] = '\0';
160	} else {
161		snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN);
162		name[GPIOMAXNAME - 1] = '\0';
163	}
164
165	return (0);
166}
167
168/* Get a specific pin's current in/out/tri state. */
169static int
170zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
171{
172	struct zy7_gpio_softc *sc = device_get_softc(dev);
173
174	if (!VALID_PIN(pin))
175		return (EINVAL);
176
177	ZGPIO_LOCK(sc);
178
179	if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
180		/* output */
181		if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
182			*flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
183		else
184			*flags = GPIO_PIN_OUTPUT;
185	} else
186		/* input */
187		*flags = GPIO_PIN_INPUT;
188
189	ZGPIO_UNLOCK(sc);
190
191	return (0);
192}
193
194/* Set a specific pin's in/out/tri state. */
195static int
196zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
197{
198	struct zy7_gpio_softc *sc = device_get_softc(dev);
199
200	if (!VALID_PIN(pin))
201		return (EINVAL);
202
203	ZGPIO_LOCK(sc);
204
205	if ((flags & GPIO_PIN_OUTPUT) != 0) {
206		/* Output.  Set or reset OEN too. */
207		WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
208		    RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
209
210		if ((flags & GPIO_PIN_TRISTATE) != 0)
211			WR4(sc, ZY7_GPIO_OEN(pin >> 5),
212			    RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
213			    ~(1 << (pin & 31)));
214		else
215			WR4(sc, ZY7_GPIO_OEN(pin >> 5),
216			    RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
217			    (1 << (pin & 31)));
218	} else {
219		/* Input.  Turn off OEN. */
220		WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
221		    RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
222		WR4(sc, ZY7_GPIO_OEN(pin >> 5),
223		    RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
224	}
225
226	ZGPIO_UNLOCK(sc);
227
228	return (0);
229}
230
231/* Set a specific output pin's value. */
232static int
233zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
234{
235	struct zy7_gpio_softc *sc = device_get_softc(dev);
236
237	if (!VALID_PIN(pin) || value > 1)
238		return (EINVAL);
239
240	/* Fancy register tricks allow atomic set or reset. */
241	if ((pin & 16) != 0)
242		WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
243		    (0xffff0000 ^ (0x10000 << (pin & 15))) |
244		    (value << (pin & 15)));
245	else
246		WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
247		    (0xffff0000 ^ (0x10000 << (pin & 15))) |
248		    (value << (pin & 15)));
249
250	return (0);
251}
252
253/* Get a specific pin's input value. */
254static int
255zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
256{
257	struct zy7_gpio_softc *sc = device_get_softc(dev);
258
259	if (!VALID_PIN(pin))
260		return (EINVAL);
261
262	*value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
263
264	return (0);
265}
266
267/* Toggle a pin's output value. */
268static int
269zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
270{
271	struct zy7_gpio_softc *sc = device_get_softc(dev);
272
273	if (!VALID_PIN(pin))
274		return (EINVAL);
275
276	ZGPIO_LOCK(sc);
277
278	WR4(sc, ZY7_GPIO_DATA(pin >> 5),
279	    RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
280
281	ZGPIO_UNLOCK(sc);
282
283	return (0);
284}
285
286static int
287zy7_gpio_probe(device_t dev)
288{
289
290	if (!ofw_bus_status_okay(dev))
291		return (ENXIO);
292
293	if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio"))
294		return (ENXIO);
295
296	device_set_desc(dev, "Zynq-7000 GPIO driver");
297	return (0);
298}
299
300static int zy7_gpio_detach(device_t dev);
301
302static int
303zy7_gpio_attach(device_t dev)
304{
305	struct zy7_gpio_softc *sc = device_get_softc(dev);
306	int rid;
307
308	sc->dev = dev;
309
310	ZGPIO_LOCK_INIT(sc);
311
312	/* Allocate memory. */
313	rid = 0;
314	sc->mem_res = bus_alloc_resource_any(dev,
315		     SYS_RES_MEMORY, &rid, RF_ACTIVE);
316	if (sc->mem_res == NULL) {
317		device_printf(dev, "Can't allocate memory for device");
318		zy7_gpio_detach(dev);
319		return (ENOMEM);
320	}
321
322	sc->busdev = gpiobus_attach_bus(dev);
323	if (sc->busdev == NULL) {
324		zy7_gpio_detach(dev);
325		return (ENOMEM);
326	}
327
328	return (0);
329}
330
331static int
332zy7_gpio_detach(device_t dev)
333{
334	struct zy7_gpio_softc *sc = device_get_softc(dev);
335
336	gpiobus_detach_bus(dev);
337
338	if (sc->mem_res != NULL) {
339		/* Release memory resource. */
340		bus_release_resource(dev, SYS_RES_MEMORY,
341				     rman_get_rid(sc->mem_res), sc->mem_res);
342	}
343
344	ZGPIO_LOCK_DESTROY(sc);
345
346	return (0);
347}
348
349static device_method_t zy7_gpio_methods[] = {
350	/* device_if */
351	DEVMETHOD(device_probe, 	zy7_gpio_probe),
352	DEVMETHOD(device_attach, 	zy7_gpio_attach),
353	DEVMETHOD(device_detach, 	zy7_gpio_detach),
354
355	/* GPIO protocol */
356	DEVMETHOD(gpio_get_bus, 	zy7_gpio_get_bus),
357	DEVMETHOD(gpio_pin_max, 	zy7_gpio_pin_max),
358	DEVMETHOD(gpio_pin_getname, 	zy7_gpio_pin_getname),
359	DEVMETHOD(gpio_pin_getflags, 	zy7_gpio_pin_getflags),
360	DEVMETHOD(gpio_pin_getcaps, 	zy7_gpio_pin_getcaps),
361	DEVMETHOD(gpio_pin_setflags, 	zy7_gpio_pin_setflags),
362	DEVMETHOD(gpio_pin_get, 	zy7_gpio_pin_get),
363	DEVMETHOD(gpio_pin_set, 	zy7_gpio_pin_set),
364	DEVMETHOD(gpio_pin_toggle, 	zy7_gpio_pin_toggle),
365
366	DEVMETHOD_END
367};
368
369static driver_t zy7_gpio_driver = {
370	"gpio",
371	zy7_gpio_methods,
372	sizeof(struct zy7_gpio_softc),
373};
374static devclass_t zy7_gpio_devclass;
375
376DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \
377	      NULL, NULL);
378