Lines Matching refs:WR4
193 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
246 WR4(sc, I2C_FIFO_CONTROL, reg);
274 WR4(sc, I2C_CLK_DIVISOR,
285 WR4(sc, I2C_BUS_CLEAR_CONFIG,
290 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
300 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
334 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
335 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
336 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
341 WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) |
344 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
376 WR4(sc, I2C_TX_PACKET_FIFO, reg);
425 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
426 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
446 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
454 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
463 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);
467 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status);
469 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
486 WR4(sc, I2C_TX_PACKET_FIFO, tmp);
489 WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1);
504 WR4(sc, I2C_TX_PACKET_FIFO, tmp);
512 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask);
580 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
581 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);