Searched refs:Vec1 (Results 1 - 8 of 8) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 581 const auto *Vec1 = cast<DependentSizedExtVectorType>(T1); local
583 if (!IsStructurallyEquivalent(Context, Vec1->getSizeExpr(),
586 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(),
593 const auto *Vec1 = cast<DependentVectorType>(T1); local
595 if (Vec1->getVectorKind() != Vec2->getVectorKind())
597 if (!IsStructurallyEquivalent(Context, Vec1->getSizeExpr(),
600 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(),
608 const auto *Vec1 = cast<VectorType>(T1); local
610 if (!IsStructurallyEquivalent(Context, Vec1->getElementType(),
613 if (Vec1
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2049 SDValue Vec1 = N->getOperand(1);
2052 Results.push(TargetOpcode::COPY, ResTy, {Vec1});
2065 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N);
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| H A D | HexagonISelLoweringHVX.cpp | 1356 SDValue Vec1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, local
1367 DAG.getNode(ISD::SUB, dl, ResTy, {InpV, Vec1})});
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 4231 Value *Vec1, *Vec2, *Mask; local
4232 if (getValueTypePair(Record, OpNum, NextValueNo, Vec1, &FullTy) ||
4233 popValue(Record, OpNum, NextValueNo, Vec1->getType(), Vec2))
4238 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy())
4241 I = new ShuffleVectorInst(Vec1, Vec2, Mask);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1889 SDValue Vec1 = IntermedVals[0].first;
1903 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
2004 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2012 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 289 Value *Vec1 = nullptr; local
311 if (!Vec1 || Vec1 == Vec)
312 Vec1 = Vec;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5404 SDValue Vec1 = SVN->getOperand(VecIdx1);
5406 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
9825 // ScalarRes = EXTRACT_VECTOR_ELT ((vector-BINOP Vec1, Vec2), Idx)
9827 // Vec1Elt = EXTRACT_VECTOR_ELT(Vec1, Idx)
10293 SDValue Vec1 = Op1.getOperand(0);
10320 if (Vec1 == Vec2 || Vec3 == Vec4)
10323 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16)
10326 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
10327 (Vec1 == Vec4 && Vec2 == Vec3)) {
10328 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | [all...] |
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