Searched refs:Src0 (Results 1 - 25 of 37) sorted by relevance

12

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DConstantFoldingMIRBuilder.h50 const SrcOp &Src0 = SrcOps[0]; variable
53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
61 const SrcOp &Src0 = SrcOps[0]; variable
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
H A DMachineIRBuilder.h1336 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, argument
1339 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1353 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, argument
1356 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1369 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, argument
1372 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1375 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, argument
1378 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1381 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, argument
1384 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src
1387 buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1393 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1399 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1405 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1411 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1417 buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1423 buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1429 buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1446 buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1461 buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1467 buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1475 buildNot(const DstOp &Dst, const SrcOp &Src0) argument
1481 buildCTPOP(const DstOp &Dst, const SrcOp &Src0) argument
1486 buildCTLZ(const DstOp &Dst, const SrcOp &Src0) argument
1491 buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) argument
1496 buildCTTZ(const DstOp &Dst, const SrcOp &Src0) argument
1501 buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) argument
1506 buildBSwap(const DstOp &Dst, const SrcOp &Src0) argument
1511 buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1518 buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1525 buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional<unsigned> Flags = None) argument
1532 buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional<unsigned> Flags = None) argument
1539 buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional<unsigned> Flags = None) argument
1545 buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional<unsigned> Flags = None) argument
1551 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional<unsigned> Flags = None) argument
1557 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional<unsigned> Flags = None) argument
1563 buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional<unsigned> Flags = None) argument
1587 buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1593 buildUITOFP(const DstOp &Dst, const SrcOp &Src0) argument
1598 buildSITOFP(const DstOp &Dst, const SrcOp &Src0) argument
1603 buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) argument
1608 buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) argument
1613 buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1619 buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1625 buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1631 buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp158 Register Src0 = local
164 (void) Src0;
166 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
168 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
210 Register Src0 = local
223 Src0 = TRI.getSubReg(Src0, SubRegIndex);
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
230 Src0 = TRI.getSubReg(Src0, SubRegIndex
[all...]
H A DSIShrinkInstructions.cpp77 // Try to fold Src0
78 MachineOperand &Src0 = MI.getOperand(Src0Idx); local
79 if (Src0.isReg()) {
80 Register Reg = Src0.getReg();
91 Src0.setSubReg(0);
92 Src0.ChangeToImmediate(MovSrc.getImm());
95 Src0.setSubReg(0);
96 Src0.ChangeToFrameIndex(MovSrc.getIndex());
99 Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(),
189 const MachineOperand &Src0 local
326 MachineOperand *Src0 = &MI.getOperand(1); local
644 MachineOperand *Src0 = &MI.getOperand(1); local
[all...]
H A DSIFoldOperands.cpp1029 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx)); local
1032 if (!Src0->isImm() && !Src1->isImm())
1038 if (Src0->isImm() && Src0->getImm() == 0) {
1057 if (Src0->isImm() && Src1->isImm()) {
1059 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1076 if (Src0->isImm() && !Src1->isImm()) {
1077 std::swap(Src0, Src1);
1139 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); local
1143 if (Src1->isIdenticalTo(*Src0)
1305 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
1421 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
1450 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
[all...]
H A DGCNDPPCombine.cpp214 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); local
215 assert(Src0);
216 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
221 DPPInst.add(*Src0);
516 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); local
518 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
523 assert(Src0 && "Src1 without Src0?");
524 if (Src1 && Src1->isIdenticalTo(*Src0)) {
534 if (Use == Src0) {
[all...]
H A DSIOptimizeExecMasking.cpp389 MachineOperand &Src0 = SaveExecInst->getOperand(1); local
394 if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
400 OtherOp = &Src0;
H A DSIInstrInfo.cpp1828 MachineOperand &Src0,
1893 MachineOperand &Src0 = MI.getOperand(Src0Idx); local
1897 if (Src0.isReg() && Src1.isReg()) {
1898 if (isOperandLegal(MI, Src1Idx, &Src0)) {
1904 } else if (Src0.isReg() && !Src1.isReg()) {
1907 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1908 } else if (!Src0.isReg() && Src1.isReg()) {
1909 if (isOperandLegal(MI, Src1Idx, &Src0))
1910 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1917 swapSourceModifiers(MI, Src0, AMDGP
1827 swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const argument
2893 const MachineOperand *Src0 = &MI.getOperand(Src0Idx); local
2905 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); local
3830 const MachineOperand &Src0 = MI.getOperand(Src0Idx); local
3843 const MachineOperand &Src0 = MI.getOperand(Src0Idx); local
3917 const MachineOperand &Src0 = MI.getOperand(Src0Idx); local
4356 MachineOperand &Src0 = MI.getOperand(Src0Idx); local
4962 Register Src0 = MI.getOperand(1).getReg(); local
5375 MachineOperand &Src0 = Inst.getOperand(2); local
5553 MachineOperand &Src0 = Inst.getOperand(1); local
5651 MachineOperand &Src0 = Inst.getOperand(1); local
5717 MachineOperand &Src0 = Inst.getOperand(1); local
5746 MachineOperand &Src0 = Inst.getOperand(1); local
5773 MachineOperand &Src0 = Inst.getOperand(1); local
5837 MachineOperand &Src0 = Inst.getOperand(1); local
5899 MachineOperand &Src0 = Inst.getOperand(1); local
5963 MachineOperand &Src0 = Inst.getOperand(1); local
6137 MachineOperand &Src0 = Inst.getOperand(1); local
[all...]
H A DSIPeepholeSDWA.cpp563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
564 auto Imm = foldToImm(*Src0);
604 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
605 auto Imm = foldToImm(*Src0);
673 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
676 if (Register::isPhysicalRegister(Src0->getReg()) ||
681 Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32);
690 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
693 auto Imm = foldToImm(*Src0);
697 ValSrc = Src0;
1038 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); local
[all...]
H A DAMDGPUPostLegalizerCombiner.cpp189 Register Src0; local
191 bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
192 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
201 MatchInfo.CvtVal = Src0;
H A DSIFixSGPRCopies.cpp709 MachineOperand &Src0 = MI.getOperand(Src0Idx);
713 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) &&
714 Src0.getReg() != AMDGPU::M0) &&
723 for (MachineOperand *MO : {&Src0, &Src1}) {
H A DSILoadStoreOptimizer.cpp1420 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); local
1424 .add(*Src0)
1583 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); local
1587 .add(*Src0)
1759 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); local
1762 auto Offset0P = extractConstOffset(*Src0);
1768 BaseLo = *Src0;
1771 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0);
1774 if (Src0->isImm())
1775 std::swap(Src0, Src
[all...]
H A DSIISelLowering.cpp3755 MachineOperand &Src0 = MI.getOperand(2); local
3761 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3779 MachineOperand &Src0 = MI.getOperand(1); local
3786 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3788 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
3827 MachineOperand &Src0 = MI.getOperand(1); local
3830 const TargetRegisterClass *Src0RC = Src0.isReg()
3831 ? MRI.getRegClass(Src0.getReg())
3843 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
3848 MI, MRI, Src0, Src0R
3890 MachineOperand &Src0 = MI.getOperand(2); local
4043 Register Src0 = MI.getOperand(1).getReg(); local
4685 SDValue Src0 = N->getOperand(1); local
4697 SDValue Src0 = N->getOperand(1); local
6458 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator; local
7272 SDValue Src0 = Op.getOperand(4); local
8097 SDValue Src0 = Op.getOperand(0); local
9719 SDValue Src0 = N->getOperand(0); local
9756 SDValue Src0 = N->getOperand(0); local
10889 SDValue Src0 = Node->getOperand(0); local
[all...]
H A DAMDGPUInstructionSelector.cpp290 MachineOperand &Src0 = I.getOperand(1); local
311 if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg()))
312 MRI->setRegClass(Src0.getReg(), RC);
642 Register Src0 = MI.getOperand(1).getReg();
644 if (MRI->getType(Src0) != S32)
657 RBI.constrainGenericRegister(Src0, AMDGPU::SReg_32RegClass, *MRI);
676 Src0, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc0), m_ICst(ShiftAmt)))) &&
784 Register Src0 = MI.getOperand(2).getReg(); local
788 !RBI.constrainGenericRegister(Src0, AMDGP
846 Register Src0 = ChooseDenom != 0 ? Numer : Denom; local
2609 normalizeVOP3PMask(int NewMask[2], Register Src0, Register Src1, ArrayRef<int> Mask) argument
[all...]
H A DGCNHazardRecognizer.cpp896 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
897 Register Reg = Src0->getReg();
898 bool IsUndef = Src0->isUndef();
H A DAMDGPURegisterBankInfo.cpp1356 Register Src0 = getSrcRegIgnoringCopies(*MRI, Add->getOperand(1).getReg()); local
1359 const RegisterBank *Src0Bank = RBI.getRegBank(Src0, *MRI, *RBI.TRI);
1363 VOffsetReg = Src0;
1370 SOffsetReg = Src0;
1621 Register Dst, Register Src0,
1624 auto Cmp = B.buildICmp(Pred, CmpType, Src0, Src1);
1625 return B.buildSelect(Dst, Cmp, Src0, Src1);
1632 Register Src0 = MI.getOperand(1).getReg(); local
1636 MachineInstr *Sel = buildExpandedScalarMinMax(B, Pred, Dst, Src0, Src1);
2426 Register Src0 local
1619 buildExpandedScalarMinMax(MachineIRBuilder &B, CmpInst::Predicate Pred, Register Dst, Register Src0, Register Src1) argument
[all...]
H A DAMDGPUPromoteAlloca.cpp936 Value *Src0 = CI->getOperand(0); local
937 Type *EltTy = Src0->getType()->getPointerElementType();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; local
309 Src0 = MOSrc0->getReg();
311 // Src0 is going to be reused, thus, it cannot be killed anymore.
330 // Src0 is going to be reused, thus, it cannot be killed anymore.
341 if (!Src0) {
343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
344 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0);
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1443 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, argument
1445 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2);
1447 APFloat::cmpResult Cmp0 = Max3.compare(Src0);
1455 return maxnum(Src0, Src2);
1457 return maxnum(Src0, Src1);
2355 Value *Src0 = II->getArgOperand(0);
2358 if (match(Src0, m_FNeg(m_Value(X))) && match(Src1, m_FNeg(m_Value(Y)))) {
2365 if (match(Src0, m_FAbs(m_Value(X))) &&
2388 return BinaryOperator::CreateFMulFMF(Src0, Src1, II);
3592 Value *Src0 local
3669 Value *Src0 = II->getArgOperand(0); local
3697 Value *Src0 = II->getArgOperand(0); local
3792 Value *Src0 = II->getArgOperand(0); local
3865 Value *Src0 = II->getArgOperand(0); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DInferAddressSpaces.cpp633 Constant *Src0 = CE->getOperand(1); local
635 if (Src0->getType()->getPointerAddressSpace() ==
639 CE->getOperand(0), ConstantExpr::getAddrSpaceCast(Src0, TargetType),
823 Value *Src0 = Op.getOperand(1); local
826 auto I = InferredAddrSpace.find(Src0);
828 I->second : Src0->getType()->getPointerAddressSpace();
834 auto *C0 = dyn_cast<Constant>(Src0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp169 const SrcOp &Src0 = SrcOps[0];
172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
H A DLegalizerHelper.cpp4817 Register Src0 = MI.getOperand(1).getReg(); local
4823 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4824 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4833 Register Src0 = MI.getOperand(1).getReg(); local
4836 const LLT Src0Ty = MRI.getType(Src0);
4848 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4884 Register Src0 = MI.getOperand(1).getReg(); local
4895 if (!isKnownNeverSNaN(Src0, MRI))
4896 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, M
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DScalarizeMaskedMemIntrin.cpp132 Value *Src0 = CI->getArgOperand(3); local
164 Value *VResult = Src0;
397 Value *Src0 = CI->getArgOperand(3); local
411 Value *VResult = Src0;
/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp373 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
376 Function *F = CGF.CGM.getIntrinsic(ConstrainedIntrinsicID, Src0->getType());
377 return CGF.Builder.CreateConstrainedFPCall(F, { Src0 });
379 Function *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType());
380 return CGF.Builder.CreateCall(F, Src0);
389 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
393 Function *F = CGF.CGM.getIntrinsic(ConstrainedIntrinsicID, Src0->getType());
394 return CGF.Builder.CreateConstrainedFPCall(F, { Src0, Src1 });
396 Function *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType());
397 return CGF.Builder.CreateCall(F, { Src0, Src
406 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
443 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
453 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
464 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
476 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
489 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4156 SDValue Src0 = N0; local
4167 Src0 = N0Temp.getOperand(0);
4176 bool CanFoldLoads = Src0 != Src1;
4187 Load = Src0;
4191 std::swap(Src0, Src1);
4225 if ((Load = findBroadcastedOp(Src0, CmpSVT, ParentNode))) {
4229 std::swap(Src0, Src1);
4261 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0);
4285 SDValue Ops[] = { InMask, Src0, Tmp
[all...]

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