Lines Matching refs:Src0
3755 MachineOperand &Src0 = MI.getOperand(2);
3761 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3779 MachineOperand &Src0 = MI.getOperand(1);
3786 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3788 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
3827 MachineOperand &Src0 = MI.getOperand(1);
3830 const TargetRegisterClass *Src0RC = Src0.isReg()
3831 ? MRI.getRegClass(Src0.getReg())
3843 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
3848 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
3890 MachineOperand &Src0 = MI.getOperand(2);
3896 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
3899 .addReg(Src0.getReg());
3900 Src0.setReg(RegOp0);
3925 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
4043 Register Src0 = MI.getOperand(1).getReg();
4057 .addReg(Src0, 0, AMDGPU::sub0)
4063 .addReg(Src0, 0, AMDGPU::sub1)
4609 SDValue Src0 = N->getOperand(1);
4611 EVT CmpVT = Src0.getValueType();
4615 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4623 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4685 SDValue Src0 = N->getOperand(1);
4689 Src0, Src1);
4697 SDValue Src0 = N->getOperand(1);
4713 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4715 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
6458 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
6460 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
7272 SDValue Src0 = Op.getOperand(4);
7275 if (isTypeLegal(Src0.getValueType()))
7282 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0), // src0
8097 SDValue Src0 = Op.getOperand(0);
8100 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
8109 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
9719 SDValue Src0 = N->getOperand(0);
9723 if (isClampZeroToOne(Src0, Src1)) {
9738 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9739 std::swap(Src0, Src1);
9744 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
9745 std::swap(Src0, Src1);
9748 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
9756 SDValue Src0 = N->getOperand(0);
9758 if (Src0.isUndef() && Src1.isUndef())
10889 SDValue Src0 = Node->getOperand(0);
10893 if ((Src0.isMachineOpcode() &&
10894 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
10895 (Src0 == Src1 || Src0 == Src2))
10898 MVT VT = Src0.getValueType().getSimpleVT();
10900 getRegClassFor(VT, Src0.getNode()->isDivergent());
10906 UndefReg, Src0, SDValue());
10910 if (Src0.isMachineOpcode() &&
10911 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
10914 Src0 = Src1;
10917 Src0 = Src2;
10920 Src0 = UndefReg;
10926 SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };