Lines Matching refs:Src0
1828 MachineOperand &Src0,
1893 MachineOperand &Src0 = MI.getOperand(Src0Idx);
1897 if (Src0.isReg() && Src1.isReg()) {
1898 if (isOperandLegal(MI, Src1Idx, &Src0)) {
1904 } else if (Src0.isReg() && !Src1.isReg()) {
1907 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1908 } else if (!Src0.isReg() && Src1.isReg()) {
1909 if (isOperandLegal(MI, Src1Idx, &Src0))
1910 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1917 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2608 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2611 if (isInlineConstant(UseMI, *Src0, *ImmOp))
2623 if (Src0->isReg() && Src0->getReg() == Reg) {
2651 Src0->setReg(Src1Reg);
2652 Src0->setSubReg(Src1SubReg);
2653 Src0->setIsKill(Src1->isKill());
2679 if (Src0->isReg()) {
2683 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2686 MRI->hasOneUse(Src0->getReg())) {
2687 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2689 } else if ((Register::isPhysicalRegister(Src0->getReg()) &&
2691 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2692 (Register::isVirtualRegister(Src0->getReg()) &&
2694 RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2696 // VGPR is okay as Src0 - fallthrough
2706 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2893 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2894 if (!Src0->isReg() && !Src0->isImm())
2897 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
2905 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2918 !Src0->isReg() ||
2919 !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2927 .add(*Src0)
2938 .add(*Src0)
2942 if (auto Imm = getFoldableImm(Src0)) {
2962 .add(*Src0)
3830 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3833 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3834 if (!compareMachineOp(Src0, Src1) &&
3835 !compareMachineOp(Src0, Src2)) {
3843 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3847 if (!Src0.isReg() &&
3848 !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3917 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3921 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
4356 MachineOperand &Src0 = MI.getOperand(Src0Idx);
4365 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4366 isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4374 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4377 .add(Src0);
4378 Src0.ChangeToRegister(Reg, false);
4391 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4430 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
4443 Register Src0Reg = Src0.getReg();
4444 unsigned Src0SubReg = Src0.getSubReg();
4445 bool Src0Kill = Src0.isKill();
4448 Src0.ChangeToImmediate(Src1.getImm());
4450 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
4451 Src0.setSubReg(Src1.getSubReg());
4962 Register Src0 = MI.getOperand(1).getReg();
4964 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
5375 MachineOperand &Src0 = Inst.getOperand(2);
5386 .add(Src0)
5553 MachineOperand &Src0 = Inst.getOperand(1);
5577 if ((SCCSource != AMDGPU::SCC) && Src0.isImm() && (Src0.getImm() == -1) &&
5608 .add(Src0) // True
5651 MachineOperand &Src0 = Inst.getOperand(1);
5656 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
5660 .add(Src0)
5670 bool Src0IsSGPR = Src0.isReg() &&
5671 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5682 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5689 .add(Src0)
5693 .add(Src0)
5717 MachineOperand &Src0 = Inst.getOperand(1);
5724 .add(Src0)
5746 MachineOperand &Src0 = Inst.getOperand(1);
5756 .add(Src0)
5773 MachineOperand &Src0 = Inst.getOperand(1);
5779 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5780 MRI.getRegClass(Src0.getReg()) :
5785 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5795 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5837 MachineOperand &Src0 = Inst.getOperand(1);
5842 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5847 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5853 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5899 MachineOperand &Src0 = Inst.getOperand(1);
5906 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5907 MRI.getRegClass(Src0.getReg()) :
5917 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5921 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5963 MachineOperand &Src0 = Inst.getOperand(1);
5976 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5977 Op0 = &Src0;
5981 Op1 = &Src0;
6137 MachineOperand &Src0 = Inst.getOperand(1);
6153 .add(Src0);
6167 .add(Src0)
6176 .add(Src0);