| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = local
185 .addImm(ShiftImm);
188 .addImm(ShiftImm);
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; local
560 .addImm(ShiftImm);
563 .addImm(ShiftImm);
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| H A D | MipsISelLowering.cpp | 1647 int64_t ShiftImm = 32 - (Size * 8);
1649 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1650 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 213 uint64_t ShiftImm, bool SetFlags = false,
218 uint64_t ShiftImm, bool SetFlags = false,
246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
254 uint64_t ShiftImm);
1358 unsigned ShiftImm; local
1360 ShiftImm = 0;
1362 ShiftImm = 12;
1391 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1399 uint64_t ShiftImm, bool SetFlags,
1409 if (ShiftImm >
1395 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1438 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1595 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1735 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1854 uint64_t ShiftImm; local
1855 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1856 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1860 if (ShiftImm + Width > BitWidth)
1865 Immr = ShiftImm;
1866 Imms = ShiftImm + Width - 1;
1878 // SRL Value2, ShiftImm
1880 // with MaskImm >> ShiftImm to search for the bit width.
1884 // UBFM Value, ShiftImm, BitWide + SrlImm -1
1991 uint64_t ShiftImm;
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 853 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon4036::ARMOperand::MemoryOp
863 unsigned ShiftImm; member in struct:__anon4036::ARMOperand::PostIdxRegOp
875 unsigned ShiftImm; member in struct:__anon4036::ARMOperand::RegShiftedRegOp
881 unsigned ShiftImm; member in struct:__anon4036::ARMOperand::RegShiftedImmOp
1673 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1692 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1842 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2486 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2495 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
3526 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3540 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3690 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) argument
3709 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
5534 unsigned ShiftImm = 0; local
5879 unsigned ShiftImm = 0; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2775 unsigned ShiftImm; local
2778 ShiftImm = CI->getZExtValue();
2782 if (ShiftImm == 0 || ShiftImm >=32)
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 945 // This value is encoded as follows, if ShiftImm is the value within those
946 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
949 unsigned Size, ShiftImm; local
966 ShiftImm = MI.getOperand(OpIdx).getImm();
967 return Size + ShiftImm;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 523 unsigned ShiftImm = DefMI->getOperand(3).getImm(); local
526 unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1391 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); local
1392 if (!ShiftImm)
1395 int64_t Imm = *ShiftImm;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 5347 APInt ShiftImm = N2C->getAPIntValue();
5348 return getVScale(DL, VT, MulImm << ShiftImm);
|