Lines Matching refs:ShiftImm
853 unsigned ShiftImm; // shift for OffsetReg.
863 unsigned ShiftImm;
875 unsigned ShiftImm;
881 unsigned ShiftImm;
1673 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1692 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1842 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2486 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2495 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2886 Memory.ShiftImm, Memory.ShiftType);
3109 Memory.ShiftImm, Memory.ShiftType);
3119 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3191 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3527 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3533 Op->RegShiftedReg.ShiftImm = ShiftImm;
3541 unsigned ShiftImm, SMLoc S, SMLoc E) {
3545 Op->RegShiftedImm.ShiftImm = ShiftImm;
3692 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3699 Op->Memory.ShiftImm = ShiftImm;
3710 unsigned ShiftImm, SMLoc S, SMLoc E) {
3715 Op->PostIdxReg.ShiftImm = ShiftImm;
3843 OS << " shift-imm:" << Memory.ShiftImm;
3854 << PostIdxReg.ShiftImm;
3881 << RegShiftedImm.ShiftImm << ">";
5534 unsigned ShiftImm = 0;
5537 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5545 ShiftImm, S, E));
5879 unsigned ShiftImm = 0;
5882 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5893 ShiftType, ShiftImm, 0, isNegative,