1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file implements the ARMMCCodeEmitter class. 10// 11//===----------------------------------------------------------------------===// 12 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMFixupKinds.h" 16#include "MCTargetDesc/ARMMCExpr.h" 17#include "llvm/ADT/APFloat.h" 18#include "llvm/ADT/APInt.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/ADT/Statistic.h" 21#include "llvm/ADT/Triple.h" 22#include "llvm/MC/MCCodeEmitter.h" 23#include "llvm/MC/MCContext.h" 24#include "llvm/MC/MCExpr.h" 25#include "llvm/MC/MCFixup.h" 26#include "llvm/MC/MCInst.h" 27#include "llvm/MC/MCInstrDesc.h" 28#include "llvm/MC/MCInstrInfo.h" 29#include "llvm/MC/MCRegisterInfo.h" 30#include "llvm/MC/MCSubtargetInfo.h" 31#include "llvm/Support/Casting.h" 32#include "llvm/Support/Compiler.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include <algorithm> 37#include <cassert> 38#include <cstdint> 39#include <cstdlib> 40 41using namespace llvm; 42 43#define DEBUG_TYPE "mccodeemitter" 44 45STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 46STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 47 48namespace { 49 50class ARMMCCodeEmitter : public MCCodeEmitter { 51 const MCInstrInfo &MCII; 52 MCContext &CTX; 53 bool IsLittleEndian; 54 55public: 56 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 58 } 59 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 60 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete; 61 ~ARMMCCodeEmitter() override = default; 62 63 bool isThumb(const MCSubtargetInfo &STI) const { 64 return STI.getFeatureBits()[ARM::ModeThumb]; 65 } 66 67 bool isThumb2(const MCSubtargetInfo &STI) const { 68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 69 } 70 71 bool isTargetMachO(const MCSubtargetInfo &STI) const { 72 const Triple &TT = STI.getTargetTriple(); 73 return TT.isOSBinFormatMachO(); 74 } 75 76 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 77 78 // getBinaryCodeForInstr - TableGen'erated function for getting the 79 // binary encoding for an instruction. 80 uint64_t getBinaryCodeForInstr(const MCInst &MI, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 /// getMachineOpValue - Return binary encoding of operand. If the machine 85 /// operand requires relocation, record the relocation and return zero. 86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 91 /// the specified operand. This is used for operands with :lower16: and 92 /// :upper16: prefixes. 93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 98 unsigned &Reg, unsigned &Imm, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const; 101 102 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 103 /// BL branch target. 104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 105 SmallVectorImpl<MCFixup> &Fixups, 106 const MCSubtargetInfo &STI) const; 107 108 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 109 /// BLX branch target. 110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 111 SmallVectorImpl<MCFixup> &Fixups, 112 const MCSubtargetInfo &STI) const; 113 114 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const; 118 119 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 121 SmallVectorImpl<MCFixup> &Fixups, 122 const MCSubtargetInfo &STI) const; 123 124 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups, 127 const MCSubtargetInfo &STI) const; 128 129 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 130 /// branch target. 131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const; 134 135 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit 136 /// immediate Thumb2 direct branch target. 137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 138 SmallVectorImpl<MCFixup> &Fixups, 139 const MCSubtargetInfo &STI) const; 140 141 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 142 /// branch target. 143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 147 SmallVectorImpl<MCFixup> &Fixups, 148 const MCSubtargetInfo &STI) const; 149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 154 /// ADR label target. 155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 156 SmallVectorImpl<MCFixup> &Fixups, 157 const MCSubtargetInfo &STI) const; 158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 159 SmallVectorImpl<MCFixup> &Fixups, 160 const MCSubtargetInfo &STI) const; 161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 162 SmallVectorImpl<MCFixup> &Fixups, 163 const MCSubtargetInfo &STI) const; 164 165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 166 SmallVectorImpl<MCFixup> &Fixups, 167 const MCSubtargetInfo &STI) const; 168 169 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 170 /// operand. 171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 172 SmallVectorImpl<MCFixup> &Fixups, 173 const MCSubtargetInfo &STI) const; 174 175 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 176 /// operand. 177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const; 180 181 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 183 SmallVectorImpl<MCFixup> &Fixups, 184 const MCSubtargetInfo &STI) const; 185 186 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 187 /// operand. 188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 189 SmallVectorImpl<MCFixup> &Fixups, 190 const MCSubtargetInfo &STI) const; 191 192 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2' 193 /// operand. 194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 195 SmallVectorImpl<MCFixup> &Fixups, 196 const MCSubtargetInfo &STI) const; 197 198 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 199 /// operand. 200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 201 SmallVectorImpl<MCFixup> &Fixups, 202 const MCSubtargetInfo &STI) const; 203 204 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y' 205 /// operand. 206 template<unsigned Bits, unsigned Shift> 207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 208 SmallVectorImpl<MCFixup> &Fixups, 209 const MCSubtargetInfo &STI) const; 210 211 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 212 /// operand. 213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, 214 SmallVectorImpl<MCFixup> &Fixups, 215 const MCSubtargetInfo &STI) const; 216 217 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}' 218 /// operand. 219 template<int shift> 220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, 221 SmallVectorImpl<MCFixup> &Fixups, 222 const MCSubtargetInfo &STI) const; 223 224 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 225 /// operand as needed by load/store instructions. 226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 227 SmallVectorImpl<MCFixup> &Fixups, 228 const MCSubtargetInfo &STI) const; 229 230 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 232 SmallVectorImpl<MCFixup> &Fixups, 233 const MCSubtargetInfo &STI) const { 234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 235 switch (Mode) { 236 default: llvm_unreachable("Unknown addressing sub-mode!"); 237 case ARM_AM::da: return 0; 238 case ARM_AM::ia: return 1; 239 case ARM_AM::db: return 2; 240 case ARM_AM::ib: return 3; 241 } 242 } 243 244 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 245 /// 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 247 switch (ShOpc) { 248 case ARM_AM::no_shift: 249 case ARM_AM::lsl: return 0; 250 case ARM_AM::lsr: return 1; 251 case ARM_AM::asr: return 2; 252 case ARM_AM::ror: 253 case ARM_AM::rrx: return 3; 254 default: 255 llvm_unreachable("Invalid ShiftOpc!"); 256 } 257 } 258 259 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 261 SmallVectorImpl<MCFixup> &Fixups, 262 const MCSubtargetInfo &STI) const; 263 264 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 266 SmallVectorImpl<MCFixup> &Fixups, 267 const MCSubtargetInfo &STI) const; 268 269 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 271 SmallVectorImpl<MCFixup> &Fixups, 272 const MCSubtargetInfo &STI) const; 273 274 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 276 SmallVectorImpl<MCFixup> &Fixups, 277 const MCSubtargetInfo &STI) const; 278 279 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 280 /// operand. 281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 282 SmallVectorImpl<MCFixup> &Fixups, 283 const MCSubtargetInfo &STI) const; 284 285 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 287 SmallVectorImpl<MCFixup> &Fixups, 288 const MCSubtargetInfo &STI) const; 289 290 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 292 SmallVectorImpl<MCFixup> &Fixups, 293 const MCSubtargetInfo &STI) const; 294 295 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 297 SmallVectorImpl<MCFixup> &Fixups, 298 const MCSubtargetInfo &STI) const; 299 300 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 302 SmallVectorImpl<MCFixup> &Fixups, 303 const MCSubtargetInfo &STI) const; 304 305 /// getCCOutOpValue - Return encoding of the 's' bit. 306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 307 SmallVectorImpl<MCFixup> &Fixups, 308 const MCSubtargetInfo &STI) const { 309 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 310 // '1' respectively. 311 return MI.getOperand(Op).getReg() == ARM::CPSR; 312 } 313 314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 315 SmallVectorImpl<MCFixup> &Fixups, 316 const MCSubtargetInfo &ST) const { 317 const MCOperand &MO = MI.getOperand(Op); 318 319 // Support for fixups (MCFixup) 320 if (MO.isExpr()) { 321 const MCExpr *Expr = MO.getExpr(); 322 // Fixups resolve to plain values that need to be encoded. 323 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 324 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 325 return 0; 326 } 327 328 // Immediate is already in its encoded format 329 return MO.getImm(); 330 } 331 332 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 333 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 334 SmallVectorImpl<MCFixup> &Fixups, 335 const MCSubtargetInfo &STI) const { 336 const MCOperand &MO = MI.getOperand(Op); 337 338 // Support for fixups (MCFixup) 339 if (MO.isExpr()) { 340 const MCExpr *Expr = MO.getExpr(); 341 // Fixups resolve to plain values that need to be encoded. 342 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm); 343 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 344 return 0; 345 } 346 unsigned SoImm = MO.getImm(); 347 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 348 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 349 return Encoded; 350 } 351 352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const; 355 template<unsigned Bits, unsigned Shift> 356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, 357 SmallVectorImpl<MCFixup> &Fixups, 358 const MCSubtargetInfo &STI) const; 359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 360 SmallVectorImpl<MCFixup> &Fixups, 361 const MCSubtargetInfo &STI) const; 362 363 /// getSORegOpValue - Return an encoded so_reg shifted register value. 364 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 365 SmallVectorImpl<MCFixup> &Fixups, 366 const MCSubtargetInfo &STI) const; 367 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 368 SmallVectorImpl<MCFixup> &Fixups, 369 const MCSubtargetInfo &STI) const; 370 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 371 SmallVectorImpl<MCFixup> &Fixups, 372 const MCSubtargetInfo &STI) const; 373 374 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 375 SmallVectorImpl<MCFixup> &Fixups, 376 const MCSubtargetInfo &STI) const { 377 return 64 - MI.getOperand(Op).getImm(); 378 } 379 380 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 381 SmallVectorImpl<MCFixup> &Fixups, 382 const MCSubtargetInfo &STI) const; 383 384 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 385 SmallVectorImpl<MCFixup> &Fixups, 386 const MCSubtargetInfo &STI) const; 387 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 388 SmallVectorImpl<MCFixup> &Fixups, 389 const MCSubtargetInfo &STI) const; 390 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 391 SmallVectorImpl<MCFixup> &Fixups, 392 const MCSubtargetInfo &STI) const; 393 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 394 SmallVectorImpl<MCFixup> &Fixups, 395 const MCSubtargetInfo &STI) const; 396 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 397 SmallVectorImpl<MCFixup> &Fixups, 398 const MCSubtargetInfo &STI) const; 399 400 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 401 SmallVectorImpl<MCFixup> &Fixups, 402 const MCSubtargetInfo &STI) const; 403 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 404 SmallVectorImpl<MCFixup> &Fixups, 405 const MCSubtargetInfo &STI) const; 406 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 407 SmallVectorImpl<MCFixup> &Fixups, 408 const MCSubtargetInfo &STI) const; 409 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 410 SmallVectorImpl<MCFixup> &Fixups, 411 const MCSubtargetInfo &STI) const; 412 413 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 414 SmallVectorImpl<MCFixup> &Fixups, 415 const MCSubtargetInfo &STI) const; 416 417 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 418 unsigned EncodedValue, 419 const MCSubtargetInfo &STI) const; 420 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 421 unsigned EncodedValue, 422 const MCSubtargetInfo &STI) const; 423 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 424 unsigned EncodedValue, 425 const MCSubtargetInfo &STI) const; 426 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 427 unsigned EncodedValue, 428 const MCSubtargetInfo &STI) const; 429 430 unsigned VFPThumb2PostEncoder(const MCInst &MI, 431 unsigned EncodedValue, 432 const MCSubtargetInfo &STI) const; 433 434 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 435 SmallVectorImpl<MCFixup> &Fixups, 436 const MCSubtargetInfo &STI) const; 437 438 void EmitByte(unsigned char C, raw_ostream &OS) const { 439 OS << (char)C; 440 } 441 442 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 443 // Output the constant in little endian byte order. 444 for (unsigned i = 0; i != Size; ++i) { 445 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 446 EmitByte((Val >> Shift) & 0xff, OS); 447 } 448 } 449 450 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 451 SmallVectorImpl<MCFixup> &Fixups, 452 const MCSubtargetInfo &STI) const override; 453 454 template <bool isNeg, ARM::Fixups fixup> 455 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 456 SmallVectorImpl<MCFixup> &Fixups, 457 const MCSubtargetInfo &STI) const; 458 459 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 460 SmallVectorImpl<MCFixup> &Fixups, 461 const MCSubtargetInfo &STI) const; 462 463 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 464 SmallVectorImpl<MCFixup> &Fixups, 465 const MCSubtargetInfo &STI) const; 466 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx, 467 SmallVectorImpl<MCFixup> &Fixups, 468 const MCSubtargetInfo &STI) const; 469 template <unsigned size> 470 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 471 SmallVectorImpl<MCFixup> &Fixups, 472 const MCSubtargetInfo &STI) const; 473}; 474 475} // end anonymous namespace 476 477/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 478/// instructions, and rewrite them to their Thumb2 form if we are currently in 479/// Thumb2 mode. 480unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 481 unsigned EncodedValue, 482 const MCSubtargetInfo &STI) const { 483 if (isThumb2(STI)) { 484 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 485 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 486 // set to 1111. 487 unsigned Bit24 = EncodedValue & 0x01000000; 488 unsigned Bit28 = Bit24 << 4; 489 EncodedValue &= 0xEFFFFFFF; 490 EncodedValue |= Bit28; 491 EncodedValue |= 0x0F000000; 492 } 493 494 return EncodedValue; 495} 496 497/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 498/// instructions, and rewrite them to their Thumb2 form if we are currently in 499/// Thumb2 mode. 500unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 501 unsigned EncodedValue, 502 const MCSubtargetInfo &STI) const { 503 if (isThumb2(STI)) { 504 EncodedValue &= 0xF0FFFFFF; 505 EncodedValue |= 0x09000000; 506 } 507 508 return EncodedValue; 509} 510 511/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 512/// instructions, and rewrite them to their Thumb2 form if we are currently in 513/// Thumb2 mode. 514unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 515 unsigned EncodedValue, 516 const MCSubtargetInfo &STI) const { 517 if (isThumb2(STI)) { 518 EncodedValue &= 0x00FFFFFF; 519 EncodedValue |= 0xEE000000; 520 } 521 522 return EncodedValue; 523} 524 525/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 526/// if we are in Thumb2. 527unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 528 unsigned EncodedValue, 529 const MCSubtargetInfo &STI) const { 530 if (isThumb2(STI)) { 531 EncodedValue |= 0xC000000; // Set bits 27-26 532 } 533 534 return EncodedValue; 535} 536 537/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 538/// them to their Thumb2 form if we are currently in Thumb2 mode. 539unsigned ARMMCCodeEmitter:: 540VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 541 const MCSubtargetInfo &STI) const { 542 if (isThumb2(STI)) { 543 EncodedValue &= 0x0FFFFFFF; 544 EncodedValue |= 0xE0000000; 545 } 546 return EncodedValue; 547} 548 549/// getMachineOpValue - Return binary encoding of operand. If the machine 550/// operand requires relocation, record the relocation and return zero. 551unsigned ARMMCCodeEmitter:: 552getMachineOpValue(const MCInst &MI, const MCOperand &MO, 553 SmallVectorImpl<MCFixup> &Fixups, 554 const MCSubtargetInfo &STI) const { 555 if (MO.isReg()) { 556 unsigned Reg = MO.getReg(); 557 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 558 559 // In NEON, Q registers are encoded as 2x their register number, 560 // because they're using the same indices as the D registers they 561 // overlap. In MVE, there are no 64-bit vector instructions, so 562 // the encodings all refer to Q-registers by their literal 563 // register number. 564 565 if (STI.getFeatureBits()[ARM::HasMVEIntegerOps]) 566 return RegNo; 567 568 switch (Reg) { 569 default: 570 return RegNo; 571 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 572 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 573 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 574 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 575 return 2 * RegNo; 576 } 577 } else if (MO.isImm()) { 578 return static_cast<unsigned>(MO.getImm()); 579 } else if (MO.isFPImm()) { 580 return static_cast<unsigned>(APFloat(MO.getFPImm()) 581 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 582 } 583 584 llvm_unreachable("Unable to encode MCOperand!"); 585} 586 587/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 588bool ARMMCCodeEmitter:: 589EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 590 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 591 const MCSubtargetInfo &STI) const { 592 const MCOperand &MO = MI.getOperand(OpIdx); 593 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 594 595 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 596 597 int32_t SImm = MO1.getImm(); 598 bool isAdd = true; 599 600 // Special value for #-0 601 if (SImm == INT32_MIN) { 602 SImm = 0; 603 isAdd = false; 604 } 605 606 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 607 if (SImm < 0) { 608 SImm = -SImm; 609 isAdd = false; 610 } 611 612 Imm = SImm; 613 return isAdd; 614} 615 616/// getBranchTargetOpValue - Helper function to get the branch target operand, 617/// which is either an immediate or requires a fixup. 618static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 619 unsigned FixupKind, 620 SmallVectorImpl<MCFixup> &Fixups, 621 const MCSubtargetInfo &STI) { 622 const MCOperand &MO = MI.getOperand(OpIdx); 623 624 // If the destination is an immediate, we have nothing to do. 625 if (MO.isImm()) return MO.getImm(); 626 assert(MO.isExpr() && "Unexpected branch target type!"); 627 const MCExpr *Expr = MO.getExpr(); 628 MCFixupKind Kind = MCFixupKind(FixupKind); 629 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 630 631 // All of the information is in the fixup. 632 return 0; 633} 634 635// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 636// determined by negating them and XOR'ing them with bit 23. 637static int32_t encodeThumbBLOffset(int32_t offset) { 638 offset >>= 1; 639 uint32_t S = (offset & 0x800000) >> 23; 640 uint32_t J1 = (offset & 0x400000) >> 22; 641 uint32_t J2 = (offset & 0x200000) >> 21; 642 J1 = (~J1 & 0x1); 643 J2 = (~J2 & 0x1); 644 J1 ^= S; 645 J2 ^= S; 646 647 offset &= ~0x600000; 648 offset |= J1 << 22; 649 offset |= J2 << 21; 650 651 return offset; 652} 653 654/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 655uint32_t ARMMCCodeEmitter:: 656getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 657 SmallVectorImpl<MCFixup> &Fixups, 658 const MCSubtargetInfo &STI) const { 659 const MCOperand MO = MI.getOperand(OpIdx); 660 if (MO.isExpr()) 661 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 662 Fixups, STI); 663 return encodeThumbBLOffset(MO.getImm()); 664} 665 666/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 667/// BLX branch target. 668uint32_t ARMMCCodeEmitter:: 669getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 670 SmallVectorImpl<MCFixup> &Fixups, 671 const MCSubtargetInfo &STI) const { 672 const MCOperand MO = MI.getOperand(OpIdx); 673 if (MO.isExpr()) 674 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 675 Fixups, STI); 676 return encodeThumbBLOffset(MO.getImm()); 677} 678 679/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 680uint32_t ARMMCCodeEmitter:: 681getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 682 SmallVectorImpl<MCFixup> &Fixups, 683 const MCSubtargetInfo &STI) const { 684 const MCOperand MO = MI.getOperand(OpIdx); 685 if (MO.isExpr()) 686 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 687 Fixups, STI); 688 return (MO.getImm() >> 1); 689} 690 691/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 692uint32_t ARMMCCodeEmitter:: 693getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 694 SmallVectorImpl<MCFixup> &Fixups, 695 const MCSubtargetInfo &STI) const { 696 const MCOperand MO = MI.getOperand(OpIdx); 697 if (MO.isExpr()) 698 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 699 Fixups, STI); 700 return (MO.getImm() >> 1); 701} 702 703/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 704uint32_t ARMMCCodeEmitter:: 705getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 706 SmallVectorImpl<MCFixup> &Fixups, 707 const MCSubtargetInfo &STI) const { 708 const MCOperand MO = MI.getOperand(OpIdx); 709 if (MO.isExpr()) 710 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 711 return (MO.getImm() >> 1); 712} 713 714/// Return true if this branch has a non-always predication 715static bool HasConditionalBranch(const MCInst &MI) { 716 int NumOp = MI.getNumOperands(); 717 if (NumOp >= 2) { 718 for (int i = 0; i < NumOp-1; ++i) { 719 const MCOperand &MCOp1 = MI.getOperand(i); 720 const MCOperand &MCOp2 = MI.getOperand(i + 1); 721 if (MCOp1.isImm() && MCOp2.isReg() && 722 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 723 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 724 return true; 725 } 726 } 727 } 728 return false; 729} 730 731/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 732/// target. 733uint32_t ARMMCCodeEmitter:: 734getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 735 SmallVectorImpl<MCFixup> &Fixups, 736 const MCSubtargetInfo &STI) const { 737 // FIXME: This really, really shouldn't use TargetMachine. We don't want 738 // coupling between MC and TM anywhere we can help it. 739 if (isThumb2(STI)) 740 return 741 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 742 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 743} 744 745/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 746/// target. 747uint32_t ARMMCCodeEmitter:: 748getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 749 SmallVectorImpl<MCFixup> &Fixups, 750 const MCSubtargetInfo &STI) const { 751 const MCOperand MO = MI.getOperand(OpIdx); 752 if (MO.isExpr()) { 753 if (HasConditionalBranch(MI)) 754 return ::getBranchTargetOpValue(MI, OpIdx, 755 ARM::fixup_arm_condbranch, Fixups, STI); 756 return ::getBranchTargetOpValue(MI, OpIdx, 757 ARM::fixup_arm_uncondbranch, Fixups, STI); 758 } 759 760 return MO.getImm() >> 2; 761} 762 763uint32_t ARMMCCodeEmitter:: 764getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 765 SmallVectorImpl<MCFixup> &Fixups, 766 const MCSubtargetInfo &STI) const { 767 const MCOperand MO = MI.getOperand(OpIdx); 768 if (MO.isExpr()) { 769 if (HasConditionalBranch(MI)) 770 return ::getBranchTargetOpValue(MI, OpIdx, 771 ARM::fixup_arm_condbl, Fixups, STI); 772 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 773 } 774 775 return MO.getImm() >> 2; 776} 777 778uint32_t ARMMCCodeEmitter:: 779getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 780 SmallVectorImpl<MCFixup> &Fixups, 781 const MCSubtargetInfo &STI) const { 782 const MCOperand MO = MI.getOperand(OpIdx); 783 if (MO.isExpr()) 784 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 785 786 return MO.getImm() >> 1; 787} 788 789/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 790/// immediate branch target. 791uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue( 792 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 793 const MCSubtargetInfo &STI) const { 794 unsigned Val = 0; 795 const MCOperand MO = MI.getOperand(OpIdx); 796 797 if(MO.isExpr()) 798 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 799 else 800 Val = MO.getImm() >> 1; 801 802 bool I = (Val & 0x800000); 803 bool J1 = (Val & 0x400000); 804 bool J2 = (Val & 0x200000); 805 if (I ^ J1) 806 Val &= ~0x400000; 807 else 808 Val |= 0x400000; 809 810 if (I ^ J2) 811 Val &= ~0x200000; 812 else 813 Val |= 0x200000; 814 815 return Val; 816} 817 818/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 819/// ADR label target. 820uint32_t ARMMCCodeEmitter:: 821getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 822 SmallVectorImpl<MCFixup> &Fixups, 823 const MCSubtargetInfo &STI) const { 824 const MCOperand MO = MI.getOperand(OpIdx); 825 if (MO.isExpr()) 826 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 827 Fixups, STI); 828 int64_t offset = MO.getImm(); 829 uint32_t Val = 0x2000; 830 831 int SoImmVal; 832 if (offset == INT32_MIN) { 833 Val = 0x1000; 834 SoImmVal = 0; 835 } else if (offset < 0) { 836 Val = 0x1000; 837 offset *= -1; 838 SoImmVal = ARM_AM::getSOImmVal(offset); 839 if(SoImmVal == -1) { 840 Val = 0x2000; 841 offset *= -1; 842 SoImmVal = ARM_AM::getSOImmVal(offset); 843 } 844 } else { 845 SoImmVal = ARM_AM::getSOImmVal(offset); 846 if(SoImmVal == -1) { 847 Val = 0x1000; 848 offset *= -1; 849 SoImmVal = ARM_AM::getSOImmVal(offset); 850 } 851 } 852 853 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 854 855 Val |= SoImmVal; 856 return Val; 857} 858 859/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 860/// target. 861uint32_t ARMMCCodeEmitter:: 862getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 863 SmallVectorImpl<MCFixup> &Fixups, 864 const MCSubtargetInfo &STI) const { 865 const MCOperand MO = MI.getOperand(OpIdx); 866 if (MO.isExpr()) 867 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 868 Fixups, STI); 869 int32_t Val = MO.getImm(); 870 if (Val == INT32_MIN) 871 Val = 0x1000; 872 else if (Val < 0) { 873 Val *= -1; 874 Val |= 0x1000; 875 } 876 return Val; 877} 878 879/// getITMaskOpValue - Return the architectural encoding of an IT 880/// predication mask, given the MCOperand format. 881uint32_t ARMMCCodeEmitter:: 882getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 883 SmallVectorImpl<MCFixup> &Fixups, 884 const MCSubtargetInfo &STI) const { 885 const MCOperand MaskMO = MI.getOperand(OpIdx); 886 assert(MaskMO.isImm() && "Unexpected operand type!"); 887 888 unsigned Mask = MaskMO.getImm(); 889 890 // IT masks are encoded as a sequence of replacement low-order bits 891 // for the condition code. So if the low bit of the starting 892 // condition code is 1, then we have to flip all the bits above the 893 // terminating bit (which is the lowest 1 bit). 894 assert(OpIdx > 0 && "IT mask appears first!"); 895 const MCOperand CondMO = MI.getOperand(OpIdx-1); 896 assert(CondMO.isImm() && "Unexpected operand type!"); 897 if (CondMO.getImm() & 1) { 898 unsigned LowBit = Mask & -Mask; 899 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 900 Mask ^= BitsAboveLowBit; 901 } 902 903 return Mask; 904} 905 906/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 907/// target. 908uint32_t ARMMCCodeEmitter:: 909getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 910 SmallVectorImpl<MCFixup> &Fixups, 911 const MCSubtargetInfo &STI) const { 912 const MCOperand MO = MI.getOperand(OpIdx); 913 if (MO.isExpr()) 914 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 915 Fixups, STI); 916 return MO.getImm(); 917} 918 919/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 920/// operand. 921uint32_t ARMMCCodeEmitter:: 922getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 923 SmallVectorImpl<MCFixup> &, 924 const MCSubtargetInfo &STI) const { 925 // [Rn, Rm] 926 // {5-3} = Rm 927 // {2-0} = Rn 928 const MCOperand &MO1 = MI.getOperand(OpIdx); 929 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 930 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 931 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 932 return (Rm << 3) | Rn; 933} 934 935/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 936/// operand. 937uint32_t 938ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 939 SmallVectorImpl<MCFixup> &Fixups, 940 const MCSubtargetInfo &STI) const { 941 // {4-0} = szimm5 942 // The value we are trying to encode is an immediate between either the 943 // range of [1-7] or [1-15] depending on whether we are dealing with the 944 // u8/s8 or the u16/s16 variants respectively. 945 // This value is encoded as follows, if ShiftImm is the value within those 946 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8 947 // or 16. 948 949 unsigned Size, ShiftImm; 950 switch(MI.getOpcode()) { 951 case ARM::MVE_VSHLL_imms16bh: 952 case ARM::MVE_VSHLL_imms16th: 953 case ARM::MVE_VSHLL_immu16bh: 954 case ARM::MVE_VSHLL_immu16th: 955 Size = 16; 956 break; 957 case ARM::MVE_VSHLL_imms8bh: 958 case ARM::MVE_VSHLL_imms8th: 959 case ARM::MVE_VSHLL_immu8bh: 960 case ARM::MVE_VSHLL_immu8th: 961 Size = 8; 962 break; 963 default: 964 llvm_unreachable("Use of operand not supported by this instruction"); 965 } 966 ShiftImm = MI.getOperand(OpIdx).getImm(); 967 return Size + ShiftImm; 968} 969 970/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 971uint32_t ARMMCCodeEmitter:: 972getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 973 SmallVectorImpl<MCFixup> &Fixups, 974 const MCSubtargetInfo &STI) const { 975 // {17-13} = reg 976 // {12} = (U)nsigned (add == '1', sub == '0') 977 // {11-0} = imm12 978 unsigned Reg, Imm12; 979 bool isAdd = true; 980 // If The first operand isn't a register, we have a label reference. 981 const MCOperand &MO = MI.getOperand(OpIdx); 982 if (!MO.isReg()) { 983 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 984 Imm12 = 0; 985 986 if (MO.isExpr()) { 987 const MCExpr *Expr = MO.getExpr(); 988 isAdd = false ; // 'U' bit is set as part of the fixup. 989 990 MCFixupKind Kind; 991 if (isThumb2(STI)) 992 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 993 else 994 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 995 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 996 997 ++MCNumCPRelocations; 998 } else { 999 Reg = ARM::PC; 1000 int32_t Offset = MO.getImm(); 1001 if (Offset == INT32_MIN) { 1002 Offset = 0; 1003 isAdd = false; 1004 } else if (Offset < 0) { 1005 Offset *= -1; 1006 isAdd = false; 1007 } 1008 Imm12 = Offset; 1009 } 1010 } else 1011 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 1012 1013 uint32_t Binary = Imm12 & 0xfff; 1014 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1015 if (isAdd) 1016 Binary |= (1 << 12); 1017 Binary |= (Reg << 13); 1018 return Binary; 1019} 1020 1021template<unsigned Bits, unsigned Shift> 1022uint32_t ARMMCCodeEmitter:: 1023getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 1024 SmallVectorImpl<MCFixup> &Fixups, 1025 const MCSubtargetInfo &STI) const { 1026 // FIXME: The immediate operand should have already been encoded like this 1027 // before ever getting here. The encoder method should just need to combine 1028 // the MI operands for the register and the offset into a single 1029 // representation for the complex operand in the .td file. This isn't just 1030 // style, unfortunately. As-is, we can't represent the distinct encoding 1031 // for #-0. 1032 1033 // {Bits} = (U)nsigned (add == '1', sub == '0') 1034 // {(Bits-1)-0} = immediate 1035 int32_t Imm = MI.getOperand(OpIdx).getImm(); 1036 bool isAdd = Imm >= 0; 1037 1038 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1039 if (Imm < 0) 1040 Imm = -(uint32_t)Imm; 1041 1042 Imm >>= Shift; 1043 1044 uint32_t Binary = Imm & ((1U << Bits) - 1); 1045 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1046 if (isAdd) 1047 Binary |= (1U << Bits); 1048 return Binary; 1049} 1050 1051/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 1052/// operand. 1053uint32_t ARMMCCodeEmitter:: 1054getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, 1055 SmallVectorImpl<MCFixup> &Fixups, 1056 const MCSubtargetInfo &STI) const { 1057 // {6-3} Rn 1058 // {2-0} Qm 1059 const MCOperand &M0 = MI.getOperand(OpIdx); 1060 const MCOperand &M1 = MI.getOperand(OpIdx + 1); 1061 1062 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); 1063 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); 1064 1065 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); 1066 1067 return (Rn << 3) | Qm; 1068} 1069 1070/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 1071/// operand. 1072template<int shift> 1073uint32_t ARMMCCodeEmitter:: 1074getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, 1075 SmallVectorImpl<MCFixup> &Fixups, 1076 const MCSubtargetInfo &STI) const { 1077 // {10-8} Qm 1078 // {7-0} Imm 1079 const MCOperand &M0 = MI.getOperand(OpIdx); 1080 const MCOperand &M1 = MI.getOperand(OpIdx + 1); 1081 1082 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); 1083 int32_t Imm = M1.getImm(); 1084 1085 bool isAdd = Imm >= 0; 1086 1087 Imm >>= shift; 1088 1089 if (!isAdd) 1090 Imm = -(uint32_t)Imm; 1091 1092 Imm &= 0x7f; 1093 1094 if (isAdd) 1095 Imm |= 0x80; 1096 1097 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); 1098 1099 return (Qm << 8) | Imm; 1100} 1101 1102/// getT2AddrModeImm8s4OpValue - Return encoding info for 1103/// 'reg +/- imm8<<2' operand. 1104uint32_t ARMMCCodeEmitter:: 1105getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 1106 SmallVectorImpl<MCFixup> &Fixups, 1107 const MCSubtargetInfo &STI) const { 1108 // {12-9} = reg 1109 // {8} = (U)nsigned (add == '1', sub == '0') 1110 // {7-0} = imm8 1111 unsigned Reg, Imm8; 1112 bool isAdd = true; 1113 // If The first operand isn't a register, we have a label reference. 1114 const MCOperand &MO = MI.getOperand(OpIdx); 1115 if (!MO.isReg()) { 1116 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1117 Imm8 = 0; 1118 isAdd = false ; // 'U' bit is set as part of the fixup. 1119 1120 assert(MO.isExpr() && "Unexpected machine operand type!"); 1121 const MCExpr *Expr = MO.getExpr(); 1122 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1123 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1124 1125 ++MCNumCPRelocations; 1126 } else 1127 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1128 1129 // FIXME: The immediate operand should have already been encoded like this 1130 // before ever getting here. The encoder method should just need to combine 1131 // the MI operands for the register and the offset into a single 1132 // representation for the complex operand in the .td file. This isn't just 1133 // style, unfortunately. As-is, we can't represent the distinct encoding 1134 // for #-0. 1135 uint32_t Binary = (Imm8 >> 2) & 0xff; 1136 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1137 if (isAdd) 1138 Binary |= (1 << 8); 1139 Binary |= (Reg << 9); 1140 return Binary; 1141} 1142 1143/// getT2AddrModeImm7s4OpValue - Return encoding info for 1144/// 'reg +/- imm7<<2' operand. 1145uint32_t 1146ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 1147 SmallVectorImpl<MCFixup> &Fixups, 1148 const MCSubtargetInfo &STI) const { 1149 // {11-8} = reg 1150 // {7} = (A)dd (add == '1', sub == '0') 1151 // {6-0} = imm7 1152 unsigned Reg, Imm7; 1153 // If The first operand isn't a register, we have a label reference. 1154 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI); 1155 1156 // FIXME: The immediate operand should have already been encoded like this 1157 // before ever getting here. The encoder method should just need to combine 1158 // the MI operands for the register and the offset into a single 1159 // representation for the complex operand in the .td file. This isn't just 1160 // style, unfortunately. As-is, we can't represent the distinct encoding 1161 // for #-0. 1162 uint32_t Binary = (Imm7 >> 2) & 0xff; 1163 // Immediate is always encoded as positive. The 'A' bit controls add vs sub. 1164 if (isAdd) 1165 Binary |= (1 << 7); 1166 Binary |= (Reg << 8); 1167 return Binary; 1168} 1169 1170/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 1171/// 'reg + imm8<<2' operand. 1172uint32_t ARMMCCodeEmitter:: 1173getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 1174 SmallVectorImpl<MCFixup> &Fixups, 1175 const MCSubtargetInfo &STI) const { 1176 // {11-8} = reg 1177 // {7-0} = imm8 1178 const MCOperand &MO = MI.getOperand(OpIdx); 1179 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1180 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1181 unsigned Imm8 = MO1.getImm(); 1182 return (Reg << 8) | Imm8; 1183} 1184 1185uint32_t 1186ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 1187 SmallVectorImpl<MCFixup> &Fixups, 1188 const MCSubtargetInfo &STI) const { 1189 // {20-16} = imm{15-12} 1190 // {11-0} = imm{11-0} 1191 const MCOperand &MO = MI.getOperand(OpIdx); 1192 if (MO.isImm()) 1193 // Hi / lo 16 bits already extracted during earlier passes. 1194 return static_cast<unsigned>(MO.getImm()); 1195 1196 // Handle :upper16: and :lower16: assembly prefixes. 1197 const MCExpr *E = MO.getExpr(); 1198 MCFixupKind Kind; 1199 if (E->getKind() == MCExpr::Target) { 1200 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1201 E = ARM16Expr->getSubExpr(); 1202 1203 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1204 const int64_t Value = MCE->getValue(); 1205 if (Value > UINT32_MAX) 1206 report_fatal_error("constant value truncated (limited to 32-bit)"); 1207 1208 switch (ARM16Expr->getKind()) { 1209 case ARMMCExpr::VK_ARM_HI16: 1210 return (int32_t(Value) & 0xffff0000) >> 16; 1211 case ARMMCExpr::VK_ARM_LO16: 1212 return (int32_t(Value) & 0x0000ffff); 1213 default: llvm_unreachable("Unsupported ARMFixup"); 1214 } 1215 } 1216 1217 switch (ARM16Expr->getKind()) { 1218 default: llvm_unreachable("Unsupported ARMFixup"); 1219 case ARMMCExpr::VK_ARM_HI16: 1220 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 1221 : ARM::fixup_arm_movt_hi16); 1222 break; 1223 case ARMMCExpr::VK_ARM_LO16: 1224 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 1225 : ARM::fixup_arm_movw_lo16); 1226 break; 1227 } 1228 1229 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1230 return 0; 1231 } 1232 // If the expression doesn't have :upper16: or :lower16: on it, 1233 // it's just a plain immediate expression, previously those evaluated to 1234 // the lower 16 bits of the expression regardless of whether 1235 // we have a movt or a movw, but that led to misleadingly results. 1236 // This is disallowed in the AsmParser in validateInstruction() 1237 // so this should never happen. 1238 llvm_unreachable("expression without :upper16: or :lower16:"); 1239} 1240 1241uint32_t ARMMCCodeEmitter:: 1242getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1243 SmallVectorImpl<MCFixup> &Fixups, 1244 const MCSubtargetInfo &STI) const { 1245 const MCOperand &MO = MI.getOperand(OpIdx); 1246 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1247 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1248 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1249 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1250 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1251 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1252 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1253 unsigned SBits = getShiftOp(ShOp); 1254 1255 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1256 // amount. However, it would be an easy mistake to make so check here. 1257 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1258 1259 // {16-13} = Rn 1260 // {12} = isAdd 1261 // {11-0} = shifter 1262 // {3-0} = Rm 1263 // {4} = 0 1264 // {6-5} = type 1265 // {11-7} = imm 1266 uint32_t Binary = Rm; 1267 Binary |= Rn << 13; 1268 Binary |= SBits << 5; 1269 Binary |= ShImm << 7; 1270 if (isAdd) 1271 Binary |= 1 << 12; 1272 return Binary; 1273} 1274 1275uint32_t ARMMCCodeEmitter:: 1276getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1277 SmallVectorImpl<MCFixup> &Fixups, 1278 const MCSubtargetInfo &STI) const { 1279 // {13} 1 == imm12, 0 == Rm 1280 // {12} isAdd 1281 // {11-0} imm12/Rm 1282 const MCOperand &MO = MI.getOperand(OpIdx); 1283 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1284 unsigned Imm = MO1.getImm(); 1285 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1286 bool isReg = MO.getReg() != 0; 1287 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1288 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1289 if (isReg) { 1290 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1291 Binary <<= 7; // Shift amount is bits [11:7] 1292 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1293 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1294 } 1295 return Binary | (isAdd << 12) | (isReg << 13); 1296} 1297 1298uint32_t ARMMCCodeEmitter:: 1299getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1300 SmallVectorImpl<MCFixup> &Fixups, 1301 const MCSubtargetInfo &STI) const { 1302 // {4} isAdd 1303 // {3-0} Rm 1304 const MCOperand &MO = MI.getOperand(OpIdx); 1305 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1306 bool isAdd = MO1.getImm() != 0; 1307 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1308} 1309 1310uint32_t ARMMCCodeEmitter:: 1311getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1312 SmallVectorImpl<MCFixup> &Fixups, 1313 const MCSubtargetInfo &STI) const { 1314 // {9} 1 == imm8, 0 == Rm 1315 // {8} isAdd 1316 // {7-4} imm7_4/zero 1317 // {3-0} imm3_0/Rm 1318 const MCOperand &MO = MI.getOperand(OpIdx); 1319 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1320 unsigned Imm = MO1.getImm(); 1321 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1322 bool isImm = MO.getReg() == 0; 1323 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1324 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1325 if (!isImm) 1326 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1327 return Imm8 | (isAdd << 8) | (isImm << 9); 1328} 1329 1330uint32_t ARMMCCodeEmitter:: 1331getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1332 SmallVectorImpl<MCFixup> &Fixups, 1333 const MCSubtargetInfo &STI) const { 1334 // {13} 1 == imm8, 0 == Rm 1335 // {12-9} Rn 1336 // {8} isAdd 1337 // {7-4} imm7_4/zero 1338 // {3-0} imm3_0/Rm 1339 const MCOperand &MO = MI.getOperand(OpIdx); 1340 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1341 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1342 1343 // If The first operand isn't a register, we have a label reference. 1344 if (!MO.isReg()) { 1345 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1346 1347 assert(MO.isExpr() && "Unexpected machine operand type!"); 1348 const MCExpr *Expr = MO.getExpr(); 1349 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1350 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1351 1352 ++MCNumCPRelocations; 1353 return (Rn << 9) | (1 << 13); 1354 } 1355 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1356 unsigned Imm = MO2.getImm(); 1357 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1358 bool isImm = MO1.getReg() == 0; 1359 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1360 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1361 if (!isImm) 1362 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1363 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1364} 1365 1366/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1367uint32_t ARMMCCodeEmitter:: 1368getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1369 SmallVectorImpl<MCFixup> &Fixups, 1370 const MCSubtargetInfo &STI) const { 1371 // [SP, #imm] 1372 // {7-0} = imm8 1373 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1374 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1375 "Unexpected base register!"); 1376 1377 // The immediate is already shifted for the implicit zeroes, so no change 1378 // here. 1379 return MO1.getImm() & 0xff; 1380} 1381 1382/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1383uint32_t ARMMCCodeEmitter:: 1384getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1385 SmallVectorImpl<MCFixup> &Fixups, 1386 const MCSubtargetInfo &STI) const { 1387 // [Rn, #imm] 1388 // {7-3} = imm5 1389 // {2-0} = Rn 1390 const MCOperand &MO = MI.getOperand(OpIdx); 1391 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1392 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1393 unsigned Imm5 = MO1.getImm(); 1394 return ((Imm5 & 0x1f) << 3) | Rn; 1395} 1396 1397/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1398uint32_t ARMMCCodeEmitter:: 1399getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1400 SmallVectorImpl<MCFixup> &Fixups, 1401 const MCSubtargetInfo &STI) const { 1402 const MCOperand MO = MI.getOperand(OpIdx); 1403 if (MO.isExpr()) 1404 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1405 return (MO.getImm() >> 2); 1406} 1407 1408/// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 1409uint32_t ARMMCCodeEmitter:: 1410getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1411 SmallVectorImpl<MCFixup> &Fixups, 1412 const MCSubtargetInfo &STI) const { 1413 // {12-9} = reg 1414 // {8} = (U)nsigned (add == '1', sub == '0') 1415 // {7-0} = imm8 1416 unsigned Reg, Imm8; 1417 bool isAdd; 1418 // If The first operand isn't a register, we have a label reference. 1419 const MCOperand &MO = MI.getOperand(OpIdx); 1420 if (!MO.isReg()) { 1421 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1422 Imm8 = 0; 1423 isAdd = false; // 'U' bit is handled as part of the fixup. 1424 1425 assert(MO.isExpr() && "Unexpected machine operand type!"); 1426 const MCExpr *Expr = MO.getExpr(); 1427 MCFixupKind Kind; 1428 if (isThumb2(STI)) 1429 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1430 else 1431 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1432 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1433 1434 ++MCNumCPRelocations; 1435 } else { 1436 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1437 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1438 } 1439 1440 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1441 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1442 if (isAdd) 1443 Binary |= (1 << 8); 1444 Binary |= (Reg << 9); 1445 return Binary; 1446} 1447 1448/// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 1449uint32_t ARMMCCodeEmitter:: 1450getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 1451 SmallVectorImpl<MCFixup> &Fixups, 1452 const MCSubtargetInfo &STI) const { 1453 // {12-9} = reg 1454 // {8} = (U)nsigned (add == '1', sub == '0') 1455 // {7-0} = imm8 1456 unsigned Reg, Imm8; 1457 bool isAdd; 1458 // If The first operand isn't a register, we have a label reference. 1459 const MCOperand &MO = MI.getOperand(OpIdx); 1460 if (!MO.isReg()) { 1461 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1462 Imm8 = 0; 1463 isAdd = false; // 'U' bit is handled as part of the fixup. 1464 1465 assert(MO.isExpr() && "Unexpected machine operand type!"); 1466 const MCExpr *Expr = MO.getExpr(); 1467 MCFixupKind Kind; 1468 if (isThumb2(STI)) 1469 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); 1470 else 1471 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); 1472 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1473 1474 ++MCNumCPRelocations; 1475 } else { 1476 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1477 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1478 } 1479 1480 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1481 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1482 if (isAdd) 1483 Binary |= (1 << 8); 1484 Binary |= (Reg << 9); 1485 return Binary; 1486} 1487 1488unsigned ARMMCCodeEmitter:: 1489getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1490 SmallVectorImpl<MCFixup> &Fixups, 1491 const MCSubtargetInfo &STI) const { 1492 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1493 // shifted. The second is Rs, the amount to shift by, and the third specifies 1494 // the type of the shift. 1495 // 1496 // {3-0} = Rm. 1497 // {4} = 1 1498 // {6-5} = type 1499 // {11-8} = Rs 1500 // {7} = 0 1501 1502 const MCOperand &MO = MI.getOperand(OpIdx); 1503 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1504 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1505 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1506 1507 // Encode Rm. 1508 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1509 1510 // Encode the shift opcode. 1511 unsigned SBits = 0; 1512 unsigned Rs = MO1.getReg(); 1513 if (Rs) { 1514 // Set shift operand (bit[7:4]). 1515 // LSL - 0001 1516 // LSR - 0011 1517 // ASR - 0101 1518 // ROR - 0111 1519 switch (SOpc) { 1520 default: llvm_unreachable("Unknown shift opc!"); 1521 case ARM_AM::lsl: SBits = 0x1; break; 1522 case ARM_AM::lsr: SBits = 0x3; break; 1523 case ARM_AM::asr: SBits = 0x5; break; 1524 case ARM_AM::ror: SBits = 0x7; break; 1525 } 1526 } 1527 1528 Binary |= SBits << 4; 1529 1530 // Encode the shift operation Rs. 1531 // Encode Rs bit[11:8]. 1532 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1533 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1534} 1535 1536unsigned ARMMCCodeEmitter:: 1537getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1538 SmallVectorImpl<MCFixup> &Fixups, 1539 const MCSubtargetInfo &STI) const { 1540 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1541 // shifted. The second is the amount to shift by. 1542 // 1543 // {3-0} = Rm. 1544 // {4} = 0 1545 // {6-5} = type 1546 // {11-7} = imm 1547 1548 const MCOperand &MO = MI.getOperand(OpIdx); 1549 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1550 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1551 1552 // Encode Rm. 1553 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1554 1555 // Encode the shift opcode. 1556 unsigned SBits = 0; 1557 1558 // Set shift operand (bit[6:4]). 1559 // LSL - 000 1560 // LSR - 010 1561 // ASR - 100 1562 // ROR - 110 1563 // RRX - 110 and bit[11:8] clear. 1564 switch (SOpc) { 1565 default: llvm_unreachable("Unknown shift opc!"); 1566 case ARM_AM::lsl: SBits = 0x0; break; 1567 case ARM_AM::lsr: SBits = 0x2; break; 1568 case ARM_AM::asr: SBits = 0x4; break; 1569 case ARM_AM::ror: SBits = 0x6; break; 1570 case ARM_AM::rrx: 1571 Binary |= 0x60; 1572 return Binary; 1573 } 1574 1575 // Encode shift_imm bit[11:7]. 1576 Binary |= SBits << 4; 1577 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1578 assert(Offset < 32 && "Offset must be in range 0-31!"); 1579 return Binary | (Offset << 7); 1580} 1581 1582 1583unsigned ARMMCCodeEmitter:: 1584getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1585 SmallVectorImpl<MCFixup> &Fixups, 1586 const MCSubtargetInfo &STI) const { 1587 const MCOperand &MO1 = MI.getOperand(OpNum); 1588 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1589 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1590 1591 // Encoded as [Rn, Rm, imm]. 1592 // FIXME: Needs fixup support. 1593 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1594 Value <<= 4; 1595 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1596 Value <<= 2; 1597 Value |= MO3.getImm(); 1598 1599 return Value; 1600} 1601 1602template<unsigned Bits, unsigned Shift> 1603unsigned ARMMCCodeEmitter:: 1604getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, 1605 SmallVectorImpl<MCFixup> &Fixups, 1606 const MCSubtargetInfo &STI) const { 1607 const MCOperand &MO1 = MI.getOperand(OpNum); 1608 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1609 1610 // FIXME: Needs fixup support. 1611 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1612 1613 // If the immediate is B bits long, we need B+1 bits in order 1614 // to represent the (inverse of the) sign bit. 1615 Value <<= (Bits + 1); 1616 int32_t tmp = (int32_t)MO2.getImm(); 1617 if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it 1618 tmp = 0; 1619 } else if (tmp < 0) { 1620 tmp = abs(tmp); 1621 } else { 1622 Value |= (1U << Bits); // Set the ADD bit 1623 } 1624 Value |= (tmp >> Shift) & ((1U << Bits) - 1); 1625 return Value; 1626} 1627 1628unsigned ARMMCCodeEmitter:: 1629getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1630 SmallVectorImpl<MCFixup> &Fixups, 1631 const MCSubtargetInfo &STI) const { 1632 const MCOperand &MO1 = MI.getOperand(OpNum); 1633 1634 // FIXME: Needs fixup support. 1635 unsigned Value = 0; 1636 int32_t tmp = (int32_t)MO1.getImm(); 1637 if (tmp < 0) 1638 tmp = abs(tmp); 1639 else 1640 Value |= 256; // Set the ADD bit 1641 Value |= tmp & 255; 1642 return Value; 1643} 1644 1645unsigned ARMMCCodeEmitter:: 1646getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1647 SmallVectorImpl<MCFixup> &Fixups, 1648 const MCSubtargetInfo &STI) const { 1649 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1650 // shifted. The second is the amount to shift by. 1651 // 1652 // {3-0} = Rm. 1653 // {4} = 0 1654 // {6-5} = type 1655 // {11-7} = imm 1656 1657 const MCOperand &MO = MI.getOperand(OpIdx); 1658 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1659 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1660 1661 // Encode Rm. 1662 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1663 1664 // Encode the shift opcode. 1665 unsigned SBits = 0; 1666 // Set shift operand (bit[6:4]). 1667 // LSL - 000 1668 // LSR - 010 1669 // ASR - 100 1670 // ROR - 110 1671 switch (SOpc) { 1672 default: llvm_unreachable("Unknown shift opc!"); 1673 case ARM_AM::lsl: SBits = 0x0; break; 1674 case ARM_AM::lsr: SBits = 0x2; break; 1675 case ARM_AM::asr: SBits = 0x4; break; 1676 case ARM_AM::rrx: LLVM_FALLTHROUGH; 1677 case ARM_AM::ror: SBits = 0x6; break; 1678 } 1679 1680 Binary |= SBits << 4; 1681 if (SOpc == ARM_AM::rrx) 1682 return Binary; 1683 1684 // Encode shift_imm bit[11:7]. 1685 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1686} 1687 1688unsigned ARMMCCodeEmitter:: 1689getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1690 SmallVectorImpl<MCFixup> &Fixups, 1691 const MCSubtargetInfo &STI) const { 1692 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the 1693 // msb of the mask. 1694 const MCOperand &MO = MI.getOperand(Op); 1695 uint32_t v = ~MO.getImm(); 1696 uint32_t lsb = countTrailingZeros(v); 1697 uint32_t msb = (32 - countLeadingZeros (v)) - 1; 1698 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1699 return lsb | (msb << 5); 1700} 1701 1702unsigned ARMMCCodeEmitter:: 1703getRegisterListOpValue(const MCInst &MI, unsigned Op, 1704 SmallVectorImpl<MCFixup> &Fixups, 1705 const MCSubtargetInfo &STI) const { 1706 // VLDM/VSTM/VSCCLRM: 1707 // {12-8} = Vd 1708 // {7-0} = Number of registers 1709 // 1710 // LDM/STM: 1711 // {15-0} = Bitfield of GPRs. 1712 unsigned Reg = MI.getOperand(Op).getReg(); 1713 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1714 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1715 1716 unsigned Binary = 0; 1717 1718 if (SPRRegs || DPRRegs) { 1719 // VLDM/VSTM/VSCCLRM 1720 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1721 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1722 Binary |= (RegNo & 0x1f) << 8; 1723 1724 // Ignore VPR 1725 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS) 1726 --NumRegs; 1727 if (SPRRegs) 1728 Binary |= NumRegs; 1729 else 1730 Binary |= NumRegs * 2; 1731 } else { 1732 const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); 1733 assert(std::is_sorted(MI.begin() + Op, MI.end(), 1734 [&](const MCOperand &LHS, const MCOperand &RHS) { 1735 return MRI.getEncodingValue(LHS.getReg()) < 1736 MRI.getEncodingValue(RHS.getReg()); 1737 })); 1738 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1739 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); 1740 Binary |= 1 << RegNo; 1741 } 1742 } 1743 1744 return Binary; 1745} 1746 1747/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1748/// with the alignment operand. 1749unsigned ARMMCCodeEmitter:: 1750getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1751 SmallVectorImpl<MCFixup> &Fixups, 1752 const MCSubtargetInfo &STI) const { 1753 const MCOperand &Reg = MI.getOperand(Op); 1754 const MCOperand &Imm = MI.getOperand(Op + 1); 1755 1756 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1757 unsigned Align = 0; 1758 1759 switch (Imm.getImm()) { 1760 default: break; 1761 case 2: 1762 case 4: 1763 case 8: Align = 0x01; break; 1764 case 16: Align = 0x02; break; 1765 case 32: Align = 0x03; break; 1766 } 1767 1768 return RegNo | (Align << 4); 1769} 1770 1771/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1772/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1773unsigned ARMMCCodeEmitter:: 1774getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1775 SmallVectorImpl<MCFixup> &Fixups, 1776 const MCSubtargetInfo &STI) const { 1777 const MCOperand &Reg = MI.getOperand(Op); 1778 const MCOperand &Imm = MI.getOperand(Op + 1); 1779 1780 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1781 unsigned Align = 0; 1782 1783 switch (Imm.getImm()) { 1784 default: break; 1785 case 8: 1786 case 16: 1787 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1788 case 2: Align = 0x00; break; 1789 case 4: Align = 0x03; break; 1790 } 1791 1792 return RegNo | (Align << 4); 1793} 1794 1795 1796/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1797/// alignment operand for use in VLD-dup instructions. This is the same as 1798/// getAddrMode6AddressOpValue except for the alignment encoding, which is 1799/// different for VLD4-dup. 1800unsigned ARMMCCodeEmitter:: 1801getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1802 SmallVectorImpl<MCFixup> &Fixups, 1803 const MCSubtargetInfo &STI) const { 1804 const MCOperand &Reg = MI.getOperand(Op); 1805 const MCOperand &Imm = MI.getOperand(Op + 1); 1806 1807 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1808 unsigned Align = 0; 1809 1810 switch (Imm.getImm()) { 1811 default: break; 1812 case 2: 1813 case 4: 1814 case 8: Align = 0x01; break; 1815 case 16: Align = 0x03; break; 1816 } 1817 1818 return RegNo | (Align << 4); 1819} 1820 1821unsigned ARMMCCodeEmitter:: 1822getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1823 SmallVectorImpl<MCFixup> &Fixups, 1824 const MCSubtargetInfo &STI) const { 1825 const MCOperand &MO = MI.getOperand(Op); 1826 if (MO.getReg() == 0) return 0x0D; 1827 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1828} 1829 1830unsigned ARMMCCodeEmitter:: 1831getShiftRight8Imm(const MCInst &MI, unsigned Op, 1832 SmallVectorImpl<MCFixup> &Fixups, 1833 const MCSubtargetInfo &STI) const { 1834 return 8 - MI.getOperand(Op).getImm(); 1835} 1836 1837unsigned ARMMCCodeEmitter:: 1838getShiftRight16Imm(const MCInst &MI, unsigned Op, 1839 SmallVectorImpl<MCFixup> &Fixups, 1840 const MCSubtargetInfo &STI) const { 1841 return 16 - MI.getOperand(Op).getImm(); 1842} 1843 1844unsigned ARMMCCodeEmitter:: 1845getShiftRight32Imm(const MCInst &MI, unsigned Op, 1846 SmallVectorImpl<MCFixup> &Fixups, 1847 const MCSubtargetInfo &STI) const { 1848 return 32 - MI.getOperand(Op).getImm(); 1849} 1850 1851unsigned ARMMCCodeEmitter:: 1852getShiftRight64Imm(const MCInst &MI, unsigned Op, 1853 SmallVectorImpl<MCFixup> &Fixups, 1854 const MCSubtargetInfo &STI) const { 1855 return 64 - MI.getOperand(Op).getImm(); 1856} 1857 1858void ARMMCCodeEmitter:: 1859encodeInstruction(const MCInst &MI, raw_ostream &OS, 1860 SmallVectorImpl<MCFixup> &Fixups, 1861 const MCSubtargetInfo &STI) const { 1862 // Pseudo instructions don't get encoded. 1863 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1864 uint64_t TSFlags = Desc.TSFlags; 1865 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1866 return; 1867 1868 int Size; 1869 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1870 Size = Desc.getSize(); 1871 else 1872 llvm_unreachable("Unexpected instruction size!"); 1873 1874 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1875 // Thumb 32-bit wide instructions need to emit the high order halfword 1876 // first. 1877 if (isThumb(STI) && Size == 4) { 1878 EmitConstant(Binary >> 16, 2, OS); 1879 EmitConstant(Binary & 0xffff, 2, OS); 1880 } else 1881 EmitConstant(Binary, Size, OS); 1882 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1883} 1884 1885template <bool isNeg, ARM::Fixups fixup> 1886uint32_t 1887ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 1888 SmallVectorImpl<MCFixup> &Fixups, 1889 const MCSubtargetInfo &STI) const { 1890 const MCOperand MO = MI.getOperand(OpIdx); 1891 if (MO.isExpr()) 1892 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI); 1893 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1); 1894} 1895 1896uint32_t 1897ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 1898 SmallVectorImpl<MCFixup> &Fixups, 1899 const MCSubtargetInfo &STI) const { 1900 const MCOperand MO = MI.getOperand(OpIdx); 1901 const MCOperand BranchMO = MI.getOperand(0); 1902 1903 if (MO.isExpr()) { 1904 assert(BranchMO.isExpr()); 1905 const MCExpr *DiffExpr = MCBinaryExpr::createSub( 1906 MO.getExpr(), BranchMO.getExpr(), CTX); 1907 MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target); 1908 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc())); 1909 return 0; 1910 } 1911 1912 assert(MO.isImm() && BranchMO.isImm()); 1913 int Diff = MO.getImm() - BranchMO.getImm(); 1914 assert(Diff == 4 || Diff == 2); 1915 1916 return Diff == 4; 1917} 1918 1919uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 1920 SmallVectorImpl<MCFixup> &Fixups, 1921 const MCSubtargetInfo &STI)const { 1922 const MCOperand MO = MI.getOperand(OpIdx); 1923 assert(MO.isImm() && "Unexpected operand type!"); 1924 1925 int Value = MO.getImm(); 1926 int Imm = 0; 1927 1928 // VPT Masks are actually encoded as a series of invert/don't invert bits, 1929 // rather than true/false bits. 1930 unsigned PrevBit = 0; 1931 for (int i = 3; i >= 0; --i) { 1932 unsigned Bit = (Value >> i) & 1; 1933 1934 // Check if we are at the end of the mask. 1935 if ((Value & ~(~0U << i)) == 0) { 1936 Imm |= (1 << i); 1937 break; 1938 } 1939 1940 // Convert the bit in the mask based on the previous bit. 1941 if (Bit != PrevBit) 1942 Imm |= (1 << i); 1943 1944 PrevBit = Bit; 1945 } 1946 1947 return Imm; 1948} 1949 1950uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue( 1951 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 1952 const MCSubtargetInfo &STI) const { 1953 1954 const MCOperand MO = MI.getOperand(OpIdx); 1955 assert(MO.isImm() && "Unexpected operand type!"); 1956 1957 switch (MO.getImm()) { 1958 default: 1959 assert(0 && "Unexpected Condition!"); 1960 return 0; 1961 case ARMCC::HS: 1962 case ARMCC::EQ: 1963 return 0; 1964 case ARMCC::HI: 1965 case ARMCC::NE: 1966 return 1; 1967 case ARMCC::GE: 1968 return 4; 1969 case ARMCC::LT: 1970 return 5; 1971 case ARMCC::GT: 1972 return 6; 1973 case ARMCC::LE: 1974 return 7; 1975 } 1976} 1977 1978uint32_t ARMMCCodeEmitter:: 1979getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 1980 SmallVectorImpl<MCFixup> &Fixups, 1981 const MCSubtargetInfo &STI) const { 1982 const MCOperand &MO = MI.getOperand(OpIdx); 1983 assert(MO.isImm() && "Unexpected operand type!"); 1984 return countTrailingZeros((uint64_t)MO.getImm()); 1985} 1986 1987template <unsigned start> 1988uint32_t ARMMCCodeEmitter:: 1989getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 1990 SmallVectorImpl<MCFixup> &Fixups, 1991 const MCSubtargetInfo &STI) const { 1992 const MCOperand MO = MI.getOperand(OpIdx); 1993 assert(MO.isImm() && "Unexpected operand type!"); 1994 1995 int Value = MO.getImm(); 1996 return Value - start; 1997} 1998 1999#include "ARMGenMCCodeEmitter.inc" 2000 2001MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 2002 const MCRegisterInfo &MRI, 2003 MCContext &Ctx) { 2004 return new ARMMCCodeEmitter(MCII, Ctx, true); 2005} 2006 2007MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 2008 const MCRegisterInfo &MRI, 2009 MCContext &Ctx) { 2010 return new ARMMCCodeEmitter(MCII, Ctx, false); 2011} 2012