Searched refs:Reg2 (Results 1 - 25 of 32) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp663 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); variable
674 Reg2 = getXRegFromWReg(Reg2);
676 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
679 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
682 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
685 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
688 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
693 Reg2 = getDRegFromBReg(Reg2);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp876 unsigned Reg2) {
885 Reg1 = Reg2;
886 Reg2 = Temp;
890 I.addOperand(MCOperand::createReg(Reg2));
896 unsigned Reg2, unsigned Reg3) {
900 I.addOperand(MCOperand::createReg(Reg2));
907 unsigned Reg2, unsigned FPReg1,
911 Reg1 = Reg2;
912 Reg2 = temp;
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg
874 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument
894 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument
905 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument
[all...]
H A DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
H A DMicroMipsSizeReduction.cpp377 // Returns true if the registers Reg1 and Reg2 are consecutive
378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { argument
388 if (Registers[i + 1] == Reg2)
407 Register Reg2 = MI2->getOperand(0).getReg(); local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
479 Register Reg2 = MI2->getOperand(1).getReg(); local
481 if (Reg1 != Reg2)
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const {
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
293 MIB3.addReg(Reg2, RegState::Kill);
H A DMipsTargetStreamer.h132 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
134 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp416 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
927 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
929 bool &HaveReg2, Register &Reg2,
956 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1004 if (parseIntegerRegister(Reg2, RegGR))
1007 if (parseRegister(Reg2))
1040 Register Reg1, Reg2; local
1047 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1066 // There must be no Reg2.
1084 // If we have Reg2, i
928 parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2, Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length, bool HasLength, bool HasVectorIndex) argument
1365 Register Reg1, Reg2; local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
193 && Reg2 != OldFMAReg) {
H A DPPCVSXSwapRemoval.cpp873 Register Reg2 = MI->getOperand(2).getReg(); local
874 MI->getOperand(1).setReg(Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h103 // Union Reg1's and Reg2's groups to form a new group.
105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp177 Register Reg2 = MI.getOperand(Idx2).getReg(); local
192 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
200 Reg0 = Reg2;
202 } else if (HasDef && Reg0 == Reg2 &&
223 CommutedMI->getOperand(Idx1).setReg(Reg2);
236 if (Register::isPhysicalRegister(Reg2))
H A DAggressiveAntiDepBreaker.cpp89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { argument
95 unsigned Group2 = GetGroup(Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp190 unsigned Reg2,
413 unsigned Reg2,
427 if (Def->modifiesRegister(Reg2, TRI))
560 unsigned Reg2 = OperandMasks[J].Reg;
569 " and " << printReg(Reg2, SubReg2) << '\n');
571 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles);
577 unsigned FreeBanks2 = getFreeBanks(Reg2, SubReg2, Mask2, UsedBanks);
582 Candidates.push(Candidate(&MI, Reg2, FreeBanks2, Weight
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h166 unsigned Reg2, bool isKill2) {
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2027 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, argument
2037 if (Reg2 == AArch64::FP)
2041 if (Reg2 == Reg1 + 1)
2046 /// Returns true if Reg1 and Reg2 cannot be paired using a ldp/stp instruction.
2050 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, argument
2053 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI);
2058 return Reg2 == AArch64::LR;
2067 unsigned Reg2 = AArch64::NoRegister; member in struct:__anon3851::RegPairInfo
2074 bool isPaired() const { return Reg2 != AArch64::NoRegister; }
2149 RPI.Reg2
2292 unsigned Reg2 = RPI.Reg2; local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp760 Register Reg2 = MI->getOperand(2).getReg(); local
763 || !isARMLowRegister(Reg2))
765 if (Reg0 != Reg2) {
795 Register Reg2 = MI->getOperand(2).getReg(); local
796 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
H A DA15SDOptimizer.cpp83 unsigned Reg2);
449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
457 .addReg(Reg2)
447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
H A DARMFastISel.cpp2792 unsigned Reg2 = 0; local
2794 Reg2 = getRegForValue(Src2Value);
2795 if (Reg2 == 0) return false;
2808 MIB.addReg(Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h99 bool contains(unsigned Reg1, unsigned Reg2) const {
103 !Register::isPhysicalRegister(Reg2))
105 return MC->contains(Reg1, Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h77 bool contains(MCRegister Reg1, MCRegister Reg2) const {
78 return contains(Reg1) && contains(Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp221 unsigned Reg2, SMLoc IDLoc,
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
233 TmpInst.addOperand(MCOperand::createReg(Reg2));
220 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
226 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1383 unsigned Reg2 = Instr.getRegister2(); local
1386 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2);
1390 Streamer.emitULEB128IntValue(Reg2);
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1401 CodeGenRegister *Reg2 = i1->second; local
1403 if (&Reg1 == Reg2)
1405 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1412 if (Reg2 == Reg3)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1761 StringRef Reg2(R2);
1765 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1905 StringRef Reg2(R2);
1909 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));

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