Lines Matching refs:Reg2
416 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
927 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
929 bool &HaveReg2, Register &Reg2,
956 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1004 if (parseIntegerRegister(Reg2, RegGR))
1007 if (parseRegister(Reg2))
1040 Register Reg1, Reg2;
1047 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1066 // There must be no Reg2.
1084 // If we have Reg2, it must be an address register.
1086 if (parseAddressRegister(Reg2))
1088 Base = Regs[Reg2.Num];
1092 // If we have Reg2, it must be an address register.
1094 if (parseAddressRegister(Reg2))
1096 Base = Regs[Reg2.Num];
1116 // If we have Reg2, it must be an address register.
1118 if (parseAddressRegister(Reg2))
1120 Base = Regs[Reg2.Num];
1130 // If we have Reg2, it must be an address register.
1132 if (parseAddressRegister(Reg2))
1134 Base = Regs[Reg2.Num];
1365 Register Reg1, Reg2;
1369 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1377 if (HaveReg2 && parseAddressRegister(Reg2))