1//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/SystemZInstPrinter.h"
10#include "MCTargetDesc/SystemZMCTargetDesc.h"
11#include "TargetInfo/SystemZTargetInfo.h"
12#include "llvm/ADT/STLExtras.h"
13#include "llvm/ADT/SmallVector.h"
14#include "llvm/ADT/StringRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstBuilder.h"
19#include "llvm/MC/MCParser/MCAsmLexer.h"
20#include "llvm/MC/MCParser/MCAsmParser.h"
21#include "llvm/MC/MCParser/MCAsmParserExtension.h"
22#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23#include "llvm/MC/MCParser/MCTargetAsmParser.h"
24#include "llvm/MC/MCStreamer.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/Casting.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/SMLoc.h"
29#include "llvm/Support/TargetRegistry.h"
30#include <algorithm>
31#include <cassert>
32#include <cstddef>
33#include <cstdint>
34#include <iterator>
35#include <memory>
36#include <string>
37
38using namespace llvm;
39
40// Return true if Expr is in the range [MinValue, MaxValue].
41static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43    int64_t Value = CE->getValue();
44    return Value >= MinValue && Value <= MaxValue;
45  }
46  return false;
47}
48
49namespace {
50
51enum RegisterKind {
52  GR32Reg,
53  GRH32Reg,
54  GR64Reg,
55  GR128Reg,
56  FP32Reg,
57  FP64Reg,
58  FP128Reg,
59  VR32Reg,
60  VR64Reg,
61  VR128Reg,
62  AR32Reg,
63  CR64Reg,
64};
65
66enum MemoryKind {
67  BDMem,
68  BDXMem,
69  BDLMem,
70  BDRMem,
71  BDVMem
72};
73
74class SystemZOperand : public MCParsedAsmOperand {
75private:
76  enum OperandKind {
77    KindInvalid,
78    KindToken,
79    KindReg,
80    KindImm,
81    KindImmTLS,
82    KindMem
83  };
84
85  OperandKind Kind;
86  SMLoc StartLoc, EndLoc;
87
88  // A string of length Length, starting at Data.
89  struct TokenOp {
90    const char *Data;
91    unsigned Length;
92  };
93
94  // LLVM register Num, which has kind Kind.  In some ways it might be
95  // easier for this class to have a register bank (general, floating-point
96  // or access) and a raw register number (0-15).  This would postpone the
97  // interpretation of the operand to the add*() methods and avoid the need
98  // for context-dependent parsing.  However, we do things the current way
99  // because of the virtual getReg() method, which needs to distinguish
100  // between (say) %r0 used as a single register and %r0 used as a pair.
101  // Context-dependent parsing can also give us slightly better error
102  // messages when invalid pairs like %r1 are used.
103  struct RegOp {
104    RegisterKind Kind;
105    unsigned Num;
106  };
107
108  // Base + Disp + Index, where Base and Index are LLVM registers or 0.
109  // MemKind says what type of memory this is and RegKind says what type
110  // the base register has (GR32Reg or GR64Reg).  Length is the operand
111  // length for D(L,B)-style operands, otherwise it is null.
112  struct MemOp {
113    unsigned Base : 12;
114    unsigned Index : 12;
115    unsigned MemKind : 4;
116    unsigned RegKind : 4;
117    const MCExpr *Disp;
118    union {
119      const MCExpr *Imm;
120      unsigned Reg;
121    } Length;
122  };
123
124  // Imm is an immediate operand, and Sym is an optional TLS symbol
125  // for use with a __tls_get_offset marker relocation.
126  struct ImmTLSOp {
127    const MCExpr *Imm;
128    const MCExpr *Sym;
129  };
130
131  union {
132    TokenOp Token;
133    RegOp Reg;
134    const MCExpr *Imm;
135    ImmTLSOp ImmTLS;
136    MemOp Mem;
137  };
138
139  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
140    // Add as immediates when possible.  Null MCExpr = 0.
141    if (!Expr)
142      Inst.addOperand(MCOperand::createImm(0));
143    else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
144      Inst.addOperand(MCOperand::createImm(CE->getValue()));
145    else
146      Inst.addOperand(MCOperand::createExpr(Expr));
147  }
148
149public:
150  SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
151      : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
152
153  // Create particular kinds of operand.
154  static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
155                                                       SMLoc EndLoc) {
156    return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
157  }
158
159  static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
160    auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
161    Op->Token.Data = Str.data();
162    Op->Token.Length = Str.size();
163    return Op;
164  }
165
166  static std::unique_ptr<SystemZOperand>
167  createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
168    auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
169    Op->Reg.Kind = Kind;
170    Op->Reg.Num = Num;
171    return Op;
172  }
173
174  static std::unique_ptr<SystemZOperand>
175  createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
176    auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
177    Op->Imm = Expr;
178    return Op;
179  }
180
181  static std::unique_ptr<SystemZOperand>
182  createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
183            const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
184            unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
185    auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
186    Op->Mem.MemKind = MemKind;
187    Op->Mem.RegKind = RegKind;
188    Op->Mem.Base = Base;
189    Op->Mem.Index = Index;
190    Op->Mem.Disp = Disp;
191    if (MemKind == BDLMem)
192      Op->Mem.Length.Imm = LengthImm;
193    if (MemKind == BDRMem)
194      Op->Mem.Length.Reg = LengthReg;
195    return Op;
196  }
197
198  static std::unique_ptr<SystemZOperand>
199  createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
200               SMLoc StartLoc, SMLoc EndLoc) {
201    auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
202    Op->ImmTLS.Imm = Imm;
203    Op->ImmTLS.Sym = Sym;
204    return Op;
205  }
206
207  // Token operands
208  bool isToken() const override {
209    return Kind == KindToken;
210  }
211  StringRef getToken() const {
212    assert(Kind == KindToken && "Not a token");
213    return StringRef(Token.Data, Token.Length);
214  }
215
216  // Register operands.
217  bool isReg() const override {
218    return Kind == KindReg;
219  }
220  bool isReg(RegisterKind RegKind) const {
221    return Kind == KindReg && Reg.Kind == RegKind;
222  }
223  unsigned getReg() const override {
224    assert(Kind == KindReg && "Not a register");
225    return Reg.Num;
226  }
227
228  // Immediate operands.
229  bool isImm() const override {
230    return Kind == KindImm;
231  }
232  bool isImm(int64_t MinValue, int64_t MaxValue) const {
233    return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
234  }
235  const MCExpr *getImm() const {
236    assert(Kind == KindImm && "Not an immediate");
237    return Imm;
238  }
239
240  // Immediate operands with optional TLS symbol.
241  bool isImmTLS() const {
242    return Kind == KindImmTLS;
243  }
244
245  const ImmTLSOp getImmTLS() const {
246    assert(Kind == KindImmTLS && "Not a TLS immediate");
247    return ImmTLS;
248  }
249
250  // Memory operands.
251  bool isMem() const override {
252    return Kind == KindMem;
253  }
254  bool isMem(MemoryKind MemKind) const {
255    return (Kind == KindMem &&
256            (Mem.MemKind == MemKind ||
257             // A BDMem can be treated as a BDXMem in which the index
258             // register field is 0.
259             (Mem.MemKind == BDMem && MemKind == BDXMem)));
260  }
261  bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
262    return isMem(MemKind) && Mem.RegKind == RegKind;
263  }
264  bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
265    return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
266  }
267  bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
268    return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
269  }
270  bool isMemDisp12Len4(RegisterKind RegKind) const {
271    return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
272  }
273  bool isMemDisp12Len8(RegisterKind RegKind) const {
274    return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
275  }
276
277  const MemOp& getMem() const {
278    assert(Kind == KindMem && "Not a Mem operand");
279    return Mem;
280  }
281
282  // Override MCParsedAsmOperand.
283  SMLoc getStartLoc() const override { return StartLoc; }
284  SMLoc getEndLoc() const override { return EndLoc; }
285  void print(raw_ostream &OS) const override;
286
287  /// getLocRange - Get the range between the first and last token of this
288  /// operand.
289  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
290
291  // Used by the TableGen code to add particular types of operand
292  // to an instruction.
293  void addRegOperands(MCInst &Inst, unsigned N) const {
294    assert(N == 1 && "Invalid number of operands");
295    Inst.addOperand(MCOperand::createReg(getReg()));
296  }
297  void addImmOperands(MCInst &Inst, unsigned N) const {
298    assert(N == 1 && "Invalid number of operands");
299    addExpr(Inst, getImm());
300  }
301  void addBDAddrOperands(MCInst &Inst, unsigned N) const {
302    assert(N == 2 && "Invalid number of operands");
303    assert(isMem(BDMem) && "Invalid operand type");
304    Inst.addOperand(MCOperand::createReg(Mem.Base));
305    addExpr(Inst, Mem.Disp);
306  }
307  void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
308    assert(N == 3 && "Invalid number of operands");
309    assert(isMem(BDXMem) && "Invalid operand type");
310    Inst.addOperand(MCOperand::createReg(Mem.Base));
311    addExpr(Inst, Mem.Disp);
312    Inst.addOperand(MCOperand::createReg(Mem.Index));
313  }
314  void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
315    assert(N == 3 && "Invalid number of operands");
316    assert(isMem(BDLMem) && "Invalid operand type");
317    Inst.addOperand(MCOperand::createReg(Mem.Base));
318    addExpr(Inst, Mem.Disp);
319    addExpr(Inst, Mem.Length.Imm);
320  }
321  void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
322    assert(N == 3 && "Invalid number of operands");
323    assert(isMem(BDRMem) && "Invalid operand type");
324    Inst.addOperand(MCOperand::createReg(Mem.Base));
325    addExpr(Inst, Mem.Disp);
326    Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
327  }
328  void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
329    assert(N == 3 && "Invalid number of operands");
330    assert(isMem(BDVMem) && "Invalid operand type");
331    Inst.addOperand(MCOperand::createReg(Mem.Base));
332    addExpr(Inst, Mem.Disp);
333    Inst.addOperand(MCOperand::createReg(Mem.Index));
334  }
335  void addImmTLSOperands(MCInst &Inst, unsigned N) const {
336    assert(N == 2 && "Invalid number of operands");
337    assert(Kind == KindImmTLS && "Invalid operand type");
338    addExpr(Inst, ImmTLS.Imm);
339    if (ImmTLS.Sym)
340      addExpr(Inst, ImmTLS.Sym);
341  }
342
343  // Used by the TableGen code to check for particular operand types.
344  bool isGR32() const { return isReg(GR32Reg); }
345  bool isGRH32() const { return isReg(GRH32Reg); }
346  bool isGRX32() const { return false; }
347  bool isGR64() const { return isReg(GR64Reg); }
348  bool isGR128() const { return isReg(GR128Reg); }
349  bool isADDR32() const { return isReg(GR32Reg); }
350  bool isADDR64() const { return isReg(GR64Reg); }
351  bool isADDR128() const { return false; }
352  bool isFP32() const { return isReg(FP32Reg); }
353  bool isFP64() const { return isReg(FP64Reg); }
354  bool isFP128() const { return isReg(FP128Reg); }
355  bool isVR32() const { return isReg(VR32Reg); }
356  bool isVR64() const { return isReg(VR64Reg); }
357  bool isVF128() const { return false; }
358  bool isVR128() const { return isReg(VR128Reg); }
359  bool isAR32() const { return isReg(AR32Reg); }
360  bool isCR64() const { return isReg(CR64Reg); }
361  bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
362  bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
363  bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
364  bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
365  bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
366  bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
367  bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
368  bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
369  bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
370  bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
371  bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
372  bool isU1Imm() const { return isImm(0, 1); }
373  bool isU2Imm() const { return isImm(0, 3); }
374  bool isU3Imm() const { return isImm(0, 7); }
375  bool isU4Imm() const { return isImm(0, 15); }
376  bool isU6Imm() const { return isImm(0, 63); }
377  bool isU8Imm() const { return isImm(0, 255); }
378  bool isS8Imm() const { return isImm(-128, 127); }
379  bool isU12Imm() const { return isImm(0, 4095); }
380  bool isU16Imm() const { return isImm(0, 65535); }
381  bool isS16Imm() const { return isImm(-32768, 32767); }
382  bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
383  bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
384  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
385};
386
387class SystemZAsmParser : public MCTargetAsmParser {
388#define GET_ASSEMBLER_HEADER
389#include "SystemZGenAsmMatcher.inc"
390
391private:
392  MCAsmParser &Parser;
393  enum RegisterGroup {
394    RegGR,
395    RegFP,
396    RegV,
397    RegAR,
398    RegCR
399  };
400  struct Register {
401    RegisterGroup Group;
402    unsigned Num;
403    SMLoc StartLoc, EndLoc;
404  };
405
406  bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
407
408  bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
409
410  OperandMatchResultTy parseRegister(OperandVector &Operands,
411                                     RegisterKind Kind);
412
413  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
414
415  bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
416                    Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
417                    bool HasLength = false, bool HasVectorIndex = false);
418  bool parseAddressRegister(Register &Reg);
419
420  bool ParseDirectiveInsn(SMLoc L);
421
422  OperandMatchResultTy parseAddress(OperandVector &Operands,
423                                    MemoryKind MemKind,
424                                    RegisterKind RegKind);
425
426  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
427                                  int64_t MaxVal, bool AllowTLS);
428
429  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
430
431public:
432  SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
433                   const MCInstrInfo &MII,
434                   const MCTargetOptions &Options)
435    : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
436    MCAsmParserExtension::Initialize(Parser);
437
438    // Alias the .word directive to .short.
439    parser.addAliasForDirective(".word", ".short");
440
441    // Initialize the set of available features.
442    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
443  }
444
445  // Override MCTargetAsmParser.
446  bool ParseDirective(AsmToken DirectiveID) override;
447  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
448  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
449                     bool RestoreOnFailure);
450  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
451                                        SMLoc &EndLoc) override;
452  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453                        SMLoc NameLoc, OperandVector &Operands) override;
454  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455                               OperandVector &Operands, MCStreamer &Out,
456                               uint64_t &ErrorInfo,
457                               bool MatchingInlineAsm) override;
458
459  // Used by the TableGen code to parse particular operand types.
460  OperandMatchResultTy parseGR32(OperandVector &Operands) {
461    return parseRegister(Operands, GR32Reg);
462  }
463  OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464    return parseRegister(Operands, GRH32Reg);
465  }
466  OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467    llvm_unreachable("GRX32 should only be used for pseudo instructions");
468  }
469  OperandMatchResultTy parseGR64(OperandVector &Operands) {
470    return parseRegister(Operands, GR64Reg);
471  }
472  OperandMatchResultTy parseGR128(OperandVector &Operands) {
473    return parseRegister(Operands, GR128Reg);
474  }
475  OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476    // For the AsmParser, we will accept %r0 for ADDR32 as well.
477    return parseRegister(Operands, GR32Reg);
478  }
479  OperandMatchResultTy parseADDR64(OperandVector &Operands) {
480    // For the AsmParser, we will accept %r0 for ADDR64 as well.
481    return parseRegister(Operands, GR64Reg);
482  }
483  OperandMatchResultTy parseADDR128(OperandVector &Operands) {
484    llvm_unreachable("Shouldn't be used as an operand");
485  }
486  OperandMatchResultTy parseFP32(OperandVector &Operands) {
487    return parseRegister(Operands, FP32Reg);
488  }
489  OperandMatchResultTy parseFP64(OperandVector &Operands) {
490    return parseRegister(Operands, FP64Reg);
491  }
492  OperandMatchResultTy parseFP128(OperandVector &Operands) {
493    return parseRegister(Operands, FP128Reg);
494  }
495  OperandMatchResultTy parseVR32(OperandVector &Operands) {
496    return parseRegister(Operands, VR32Reg);
497  }
498  OperandMatchResultTy parseVR64(OperandVector &Operands) {
499    return parseRegister(Operands, VR64Reg);
500  }
501  OperandMatchResultTy parseVF128(OperandVector &Operands) {
502    llvm_unreachable("Shouldn't be used as an operand");
503  }
504  OperandMatchResultTy parseVR128(OperandVector &Operands) {
505    return parseRegister(Operands, VR128Reg);
506  }
507  OperandMatchResultTy parseAR32(OperandVector &Operands) {
508    return parseRegister(Operands, AR32Reg);
509  }
510  OperandMatchResultTy parseCR64(OperandVector &Operands) {
511    return parseRegister(Operands, CR64Reg);
512  }
513  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
514    return parseAnyRegister(Operands);
515  }
516  OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
517    return parseAddress(Operands, BDMem, GR32Reg);
518  }
519  OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
520    return parseAddress(Operands, BDMem, GR64Reg);
521  }
522  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
523    return parseAddress(Operands, BDXMem, GR64Reg);
524  }
525  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
526    return parseAddress(Operands, BDLMem, GR64Reg);
527  }
528  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
529    return parseAddress(Operands, BDRMem, GR64Reg);
530  }
531  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
532    return parseAddress(Operands, BDVMem, GR64Reg);
533  }
534  OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
535    return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
536  }
537  OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
538    return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
539  }
540  OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
541    return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
542  }
543  OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
544    return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
545  }
546  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
547    return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
548  }
549  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
550    return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
551  }
552};
553
554} // end anonymous namespace
555
556#define GET_REGISTER_MATCHER
557#define GET_SUBTARGET_FEATURE_NAME
558#define GET_MATCHER_IMPLEMENTATION
559#define GET_MNEMONIC_SPELL_CHECKER
560#include "SystemZGenAsmMatcher.inc"
561
562// Used for the .insn directives; contains information needed to parse the
563// operands in the directive.
564struct InsnMatchEntry {
565  StringRef Format;
566  uint64_t Opcode;
567  int32_t NumOperands;
568  MatchClassKind OperandKinds[5];
569};
570
571// For equal_range comparison.
572struct CompareInsn {
573  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
574    return LHS.Format < RHS;
575  }
576  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
577    return LHS < RHS.Format;
578  }
579  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
580    return LHS.Format < RHS.Format;
581  }
582};
583
584// Table initializing information for parsing the .insn directive.
585static struct InsnMatchEntry InsnMatchTable[] = {
586  /* Format, Opcode, NumOperands, OperandKinds */
587  { "e", SystemZ::InsnE, 1,
588    { MCK_U16Imm } },
589  { "ri", SystemZ::InsnRI, 3,
590    { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
591  { "rie", SystemZ::InsnRIE, 4,
592    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
593  { "ril", SystemZ::InsnRIL, 3,
594    { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
595  { "rilu", SystemZ::InsnRILU, 3,
596    { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
597  { "ris", SystemZ::InsnRIS, 5,
598    { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
599  { "rr", SystemZ::InsnRR, 3,
600    { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
601  { "rre", SystemZ::InsnRRE, 3,
602    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
603  { "rrf", SystemZ::InsnRRF, 5,
604    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
605  { "rrs", SystemZ::InsnRRS, 5,
606    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
607  { "rs", SystemZ::InsnRS, 4,
608    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609  { "rse", SystemZ::InsnRSE, 4,
610    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
611  { "rsi", SystemZ::InsnRSI, 4,
612    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
613  { "rsy", SystemZ::InsnRSY, 4,
614    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
615  { "rx", SystemZ::InsnRX, 3,
616    { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617  { "rxe", SystemZ::InsnRXE, 3,
618    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619  { "rxf", SystemZ::InsnRXF, 4,
620    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
621  { "rxy", SystemZ::InsnRXY, 3,
622    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
623  { "s", SystemZ::InsnS, 2,
624    { MCK_U32Imm, MCK_BDAddr64Disp12 } },
625  { "si", SystemZ::InsnSI, 3,
626    { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
627  { "sil", SystemZ::InsnSIL, 3,
628    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
629  { "siy", SystemZ::InsnSIY, 3,
630    { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
631  { "ss", SystemZ::InsnSS, 4,
632    { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
633  { "sse", SystemZ::InsnSSE, 3,
634    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
635  { "ssf", SystemZ::InsnSSF, 4,
636    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
637};
638
639static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
640  if (!E)
641    return;
642  if (auto *CE = dyn_cast<MCConstantExpr>(E))
643    OS << *CE;
644  else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
645    OS << *UE;
646  else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
647    OS << *BE;
648  else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
649    OS << *SRE;
650  else
651    OS << *E;
652}
653
654void SystemZOperand::print(raw_ostream &OS) const {
655  switch (Kind) {
656  case KindToken:
657    OS << "Token:" << getToken();
658    break;
659  case KindReg:
660    OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
661    break;
662  case KindImm:
663    OS << "Imm:";
664    printMCExpr(getImm(), OS);
665    break;
666  case KindImmTLS:
667    OS << "ImmTLS:";
668    printMCExpr(getImmTLS().Imm, OS);
669    if (getImmTLS().Sym) {
670      OS << ", ";
671      printMCExpr(getImmTLS().Sym, OS);
672    }
673    break;
674  case KindMem: {
675    const MemOp &Op = getMem();
676    OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
677    if (Op.Base) {
678      OS << "(";
679      if (Op.MemKind == BDLMem)
680        OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
681      else if (Op.MemKind == BDRMem)
682        OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
683      if (Op.Index)
684        OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
685      OS << SystemZInstPrinter::getRegisterName(Op.Base);
686      OS << ")";
687    }
688    break;
689  }
690  case KindInvalid:
691    break;
692  }
693}
694
695// Parse one register of the form %<prefix><number>.
696bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
697  Reg.StartLoc = Parser.getTok().getLoc();
698
699  // Eat the % prefix.
700  if (Parser.getTok().isNot(AsmToken::Percent))
701    return Error(Parser.getTok().getLoc(), "register expected");
702  const AsmToken &PercentTok = Parser.getTok();
703  Parser.Lex();
704
705  // Expect a register name.
706  if (Parser.getTok().isNot(AsmToken::Identifier)) {
707    if (RestoreOnFailure)
708      getLexer().UnLex(PercentTok);
709    return Error(Reg.StartLoc, "invalid register");
710  }
711
712  // Check that there's a prefix.
713  StringRef Name = Parser.getTok().getString();
714  if (Name.size() < 2) {
715    if (RestoreOnFailure)
716      getLexer().UnLex(PercentTok);
717    return Error(Reg.StartLoc, "invalid register");
718  }
719  char Prefix = Name[0];
720
721  // Treat the rest of the register name as a register number.
722  if (Name.substr(1).getAsInteger(10, Reg.Num)) {
723    if (RestoreOnFailure)
724      getLexer().UnLex(PercentTok);
725    return Error(Reg.StartLoc, "invalid register");
726  }
727
728  // Look for valid combinations of prefix and number.
729  if (Prefix == 'r' && Reg.Num < 16)
730    Reg.Group = RegGR;
731  else if (Prefix == 'f' && Reg.Num < 16)
732    Reg.Group = RegFP;
733  else if (Prefix == 'v' && Reg.Num < 32)
734    Reg.Group = RegV;
735  else if (Prefix == 'a' && Reg.Num < 16)
736    Reg.Group = RegAR;
737  else if (Prefix == 'c' && Reg.Num < 16)
738    Reg.Group = RegCR;
739  else {
740    if (RestoreOnFailure)
741      getLexer().UnLex(PercentTok);
742    return Error(Reg.StartLoc, "invalid register");
743  }
744
745  Reg.EndLoc = Parser.getTok().getLoc();
746  Parser.Lex();
747  return false;
748}
749
750// Parse a register of kind Kind and add it to Operands.
751OperandMatchResultTy
752SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
753  Register Reg;
754  RegisterGroup Group;
755  switch (Kind) {
756  case GR32Reg:
757  case GRH32Reg:
758  case GR64Reg:
759  case GR128Reg:
760    Group = RegGR;
761    break;
762  case FP32Reg:
763  case FP64Reg:
764  case FP128Reg:
765    Group = RegFP;
766    break;
767  case VR32Reg:
768  case VR64Reg:
769  case VR128Reg:
770    Group = RegV;
771    break;
772  case AR32Reg:
773    Group = RegAR;
774    break;
775  case CR64Reg:
776    Group = RegCR;
777    break;
778  }
779
780  // Handle register names of the form %<prefix><number>
781  if (Parser.getTok().is(AsmToken::Percent)) {
782    if (parseRegister(Reg))
783      return MatchOperand_ParseFail;
784
785    // Check the parsed register group "Reg.Group" with the expected "Group"
786    // Have to error out if user specified wrong prefix.
787    switch (Group) {
788    case RegGR:
789    case RegFP:
790    case RegAR:
791    case RegCR:
792      if (Group != Reg.Group) {
793        Error(Reg.StartLoc, "invalid operand for instruction");
794        return MatchOperand_ParseFail;
795      }
796      break;
797    case RegV:
798      if (Reg.Group != RegV && Reg.Group != RegFP) {
799        Error(Reg.StartLoc, "invalid operand for instruction");
800        return MatchOperand_ParseFail;
801      }
802      break;
803    }
804  } else if (Parser.getTok().is(AsmToken::Integer)) {
805    if (parseIntegerRegister(Reg, Group))
806      return MatchOperand_ParseFail;
807  }
808  // Otherwise we didn't match a register operand.
809  else
810    return MatchOperand_NoMatch;
811
812  // Determine the LLVM register number according to Kind.
813  const unsigned *Regs;
814  switch (Kind) {
815  case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
816  case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
817  case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
818  case GR128Reg: Regs = SystemZMC::GR128Regs; break;
819  case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
820  case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
821  case FP128Reg: Regs = SystemZMC::FP128Regs; break;
822  case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
823  case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
824  case VR128Reg: Regs = SystemZMC::VR128Regs; break;
825  case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
826  case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
827  }
828  if (Regs[Reg.Num] == 0) {
829    Error(Reg.StartLoc, "invalid register pair");
830    return MatchOperand_ParseFail;
831  }
832
833  Operands.push_back(
834      SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
835  return MatchOperand_Success;
836}
837
838// Parse any type of register (including integers) and add it to Operands.
839OperandMatchResultTy
840SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
841  // Handle integer values.
842  if (Parser.getTok().is(AsmToken::Integer)) {
843    const MCExpr *Register;
844    SMLoc StartLoc = Parser.getTok().getLoc();
845    if (Parser.parseExpression(Register))
846      return MatchOperand_ParseFail;
847
848    if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
849      int64_t Value = CE->getValue();
850      if (Value < 0 || Value > 15) {
851        Error(StartLoc, "invalid register");
852        return MatchOperand_ParseFail;
853      }
854    }
855
856    SMLoc EndLoc =
857      SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
858
859    Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
860  }
861  else {
862    Register Reg;
863    if (parseRegister(Reg))
864      return MatchOperand_ParseFail;
865
866    // Map to the correct register kind.
867    RegisterKind Kind;
868    unsigned RegNo;
869    if (Reg.Group == RegGR) {
870      Kind = GR64Reg;
871      RegNo = SystemZMC::GR64Regs[Reg.Num];
872    }
873    else if (Reg.Group == RegFP) {
874      Kind = FP64Reg;
875      RegNo = SystemZMC::FP64Regs[Reg.Num];
876    }
877    else if (Reg.Group == RegV) {
878      Kind = VR128Reg;
879      RegNo = SystemZMC::VR128Regs[Reg.Num];
880    }
881    else if (Reg.Group == RegAR) {
882      Kind = AR32Reg;
883      RegNo = SystemZMC::AR32Regs[Reg.Num];
884    }
885    else if (Reg.Group == RegCR) {
886      Kind = CR64Reg;
887      RegNo = SystemZMC::CR64Regs[Reg.Num];
888    }
889    else {
890      return MatchOperand_ParseFail;
891    }
892
893    Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
894                                                 Reg.StartLoc, Reg.EndLoc));
895  }
896  return MatchOperand_Success;
897}
898
899bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
900                                            RegisterGroup Group) {
901  Reg.StartLoc = Parser.getTok().getLoc();
902  // We have an integer token
903  const MCExpr *Register;
904  if (Parser.parseExpression(Register))
905    return true;
906
907  const auto *CE = dyn_cast<MCConstantExpr>(Register);
908  if (!CE)
909    return true;
910
911  int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
912  int64_t Value = CE->getValue();
913  if (Value < 0 || Value > MaxRegNum) {
914    Error(Parser.getTok().getLoc(), "invalid register");
915    return true;
916  }
917
918  // Assign the Register Number
919  Reg.Num = (unsigned)Value;
920  Reg.Group = Group;
921  Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
922
923  // At this point, successfully parsed an integer register.
924  return false;
925}
926
927// Parse a memory operand into Reg1, Reg2, Disp, and Length.
928bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
929                                    bool &HaveReg2, Register &Reg2,
930                                    const MCExpr *&Disp, const MCExpr *&Length,
931                                    bool HasLength, bool HasVectorIndex) {
932  // Parse the displacement, which must always be present.
933  if (getParser().parseExpression(Disp))
934    return true;
935
936  // Parse the optional base and index.
937  HaveReg1 = false;
938  HaveReg2 = false;
939  Length = nullptr;
940
941  // If we have a scenario as below:
942  //   vgef %v0, 0(0), 0
943  // This is an example of a "BDVMem" instruction type.
944  //
945  // So when we parse this as an integer register, the register group
946  // needs to be tied to "RegV". Usually when the prefix is passed in
947  // as %<prefix><reg-number> its easy to check which group it should belong to
948  // However, if we're passing in just the integer there's no real way to
949  // "check" what register group it should belong to.
950  //
951  // When the user passes in the register as an integer, the user assumes that
952  // the compiler is responsible for substituting it as the right kind of
953  // register. Whereas, when the user specifies a "prefix", the onus is on
954  // the user to make sure they pass in the right kind of register.
955  //
956  // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
957  // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
958  // (i.e. insn is of type BDVMem) is true.
959  RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
960
961  if (getLexer().is(AsmToken::LParen)) {
962    Parser.Lex();
963
964    if (getLexer().is(AsmToken::Percent)) {
965      // Parse the first register.
966      HaveReg1 = true;
967      if (parseRegister(Reg1))
968        return true;
969    }
970    // So if we have an integer as the first token in ([tok1], ..), it could:
971    // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
972    // instructions)
973    // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
974    else if (getLexer().is(AsmToken::Integer)) {
975      if (HasLength) {
976        // Instruction has a "Length" field, safe to parse the first token as
977        // the "Length" field
978        if (getParser().parseExpression(Length))
979          return true;
980      } else {
981        // Otherwise, if the instruction has no "Length" field, parse the
982        // token as a "Register". We don't have to worry about whether the
983        // instruction is invalid here, because the caller will take care of
984        // error reporting.
985        HaveReg1 = true;
986        if (parseIntegerRegister(Reg1, RegGroup))
987          return true;
988      }
989    } else {
990      // If its not an integer or a percent token, then if the instruction
991      // is reported to have a "Length" then, parse it as "Length".
992      if (HasLength) {
993        if (getParser().parseExpression(Length))
994          return true;
995      }
996    }
997
998    // Check whether there's a second register.
999    if (getLexer().is(AsmToken::Comma)) {
1000      Parser.Lex();
1001      HaveReg2 = true;
1002
1003      if (getLexer().is(AsmToken::Integer)) {
1004        if (parseIntegerRegister(Reg2, RegGR))
1005          return true;
1006      } else {
1007        if (parseRegister(Reg2))
1008          return true;
1009      }
1010    }
1011
1012    // Consume the closing bracket.
1013    if (getLexer().isNot(AsmToken::RParen))
1014      return Error(Parser.getTok().getLoc(), "unexpected token in address");
1015    Parser.Lex();
1016  }
1017  return false;
1018}
1019
1020// Verify that Reg is a valid address register (base or index).
1021bool
1022SystemZAsmParser::parseAddressRegister(Register &Reg) {
1023  if (Reg.Group == RegV) {
1024    Error(Reg.StartLoc, "invalid use of vector addressing");
1025    return true;
1026  } else if (Reg.Group != RegGR) {
1027    Error(Reg.StartLoc, "invalid address register");
1028    return true;
1029  }
1030  return false;
1031}
1032
1033// Parse a memory operand and add it to Operands.  The other arguments
1034// are as above.
1035OperandMatchResultTy
1036SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1037                               RegisterKind RegKind) {
1038  SMLoc StartLoc = Parser.getTok().getLoc();
1039  unsigned Base = 0, Index = 0, LengthReg = 0;
1040  Register Reg1, Reg2;
1041  bool HaveReg1, HaveReg2;
1042  const MCExpr *Disp;
1043  const MCExpr *Length;
1044
1045  bool HasLength = (MemKind == BDLMem) ? true : false;
1046  bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1047  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1048                   HasVectorIndex))
1049    return MatchOperand_ParseFail;
1050
1051  const unsigned *Regs;
1052  switch (RegKind) {
1053  case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1054  case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1055  default: llvm_unreachable("invalid RegKind");
1056  }
1057
1058  switch (MemKind) {
1059  case BDMem:
1060    // If we have Reg1, it must be an address register.
1061    if (HaveReg1) {
1062      if (parseAddressRegister(Reg1))
1063        return MatchOperand_ParseFail;
1064      Base = Regs[Reg1.Num];
1065    }
1066    // There must be no Reg2.
1067    if (HaveReg2) {
1068      Error(StartLoc, "invalid use of indexed addressing");
1069      return MatchOperand_ParseFail;
1070    }
1071    break;
1072  case BDXMem:
1073    // If we have Reg1, it must be an address register.
1074    if (HaveReg1) {
1075      if (parseAddressRegister(Reg1))
1076        return MatchOperand_ParseFail;
1077      // If the are two registers, the first one is the index and the
1078      // second is the base.
1079      if (HaveReg2)
1080        Index = Regs[Reg1.Num];
1081      else
1082        Base = Regs[Reg1.Num];
1083    }
1084    // If we have Reg2, it must be an address register.
1085    if (HaveReg2) {
1086      if (parseAddressRegister(Reg2))
1087        return MatchOperand_ParseFail;
1088      Base = Regs[Reg2.Num];
1089    }
1090    break;
1091  case BDLMem:
1092    // If we have Reg2, it must be an address register.
1093    if (HaveReg2) {
1094      if (parseAddressRegister(Reg2))
1095        return MatchOperand_ParseFail;
1096      Base = Regs[Reg2.Num];
1097    }
1098    // We cannot support base+index addressing.
1099    if (HaveReg1 && HaveReg2) {
1100      Error(StartLoc, "invalid use of indexed addressing");
1101      return MatchOperand_ParseFail;
1102    }
1103    // We must have a length.
1104    if (!Length) {
1105      Error(StartLoc, "missing length in address");
1106      return MatchOperand_ParseFail;
1107    }
1108    break;
1109  case BDRMem:
1110    // We must have Reg1, and it must be a GPR.
1111    if (!HaveReg1 || Reg1.Group != RegGR) {
1112      Error(StartLoc, "invalid operand for instruction");
1113      return MatchOperand_ParseFail;
1114    }
1115    LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1116    // If we have Reg2, it must be an address register.
1117    if (HaveReg2) {
1118      if (parseAddressRegister(Reg2))
1119        return MatchOperand_ParseFail;
1120      Base = Regs[Reg2.Num];
1121    }
1122    break;
1123  case BDVMem:
1124    // We must have Reg1, and it must be a vector register.
1125    if (!HaveReg1 || Reg1.Group != RegV) {
1126      Error(StartLoc, "vector index required in address");
1127      return MatchOperand_ParseFail;
1128    }
1129    Index = SystemZMC::VR128Regs[Reg1.Num];
1130    // If we have Reg2, it must be an address register.
1131    if (HaveReg2) {
1132      if (parseAddressRegister(Reg2))
1133        return MatchOperand_ParseFail;
1134      Base = Regs[Reg2.Num];
1135    }
1136    break;
1137  }
1138
1139  SMLoc EndLoc =
1140      SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1141  Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1142                                               Index, Length, LengthReg,
1143                                               StartLoc, EndLoc));
1144  return MatchOperand_Success;
1145}
1146
1147bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1148  StringRef IDVal = DirectiveID.getIdentifier();
1149
1150  if (IDVal == ".insn")
1151    return ParseDirectiveInsn(DirectiveID.getLoc());
1152
1153  return true;
1154}
1155
1156/// ParseDirectiveInsn
1157/// ::= .insn [ format, encoding, (operands (, operands)*) ]
1158bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1159  MCAsmParser &Parser = getParser();
1160
1161  // Expect instruction format as identifier.
1162  StringRef Format;
1163  SMLoc ErrorLoc = Parser.getTok().getLoc();
1164  if (Parser.parseIdentifier(Format))
1165    return Error(ErrorLoc, "expected instruction format");
1166
1167  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1168
1169  // Find entry for this format in InsnMatchTable.
1170  auto EntryRange =
1171    std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1172                     Format, CompareInsn());
1173
1174  // If first == second, couldn't find a match in the table.
1175  if (EntryRange.first == EntryRange.second)
1176    return Error(ErrorLoc, "unrecognized format");
1177
1178  struct InsnMatchEntry *Entry = EntryRange.first;
1179
1180  // Format should match from equal_range.
1181  assert(Entry->Format == Format);
1182
1183  // Parse the following operands using the table's information.
1184  for (int i = 0; i < Entry->NumOperands; i++) {
1185    MatchClassKind Kind = Entry->OperandKinds[i];
1186
1187    SMLoc StartLoc = Parser.getTok().getLoc();
1188
1189    // Always expect commas as separators for operands.
1190    if (getLexer().isNot(AsmToken::Comma))
1191      return Error(StartLoc, "unexpected token in directive");
1192    Lex();
1193
1194    // Parse operands.
1195    OperandMatchResultTy ResTy;
1196    if (Kind == MCK_AnyReg)
1197      ResTy = parseAnyReg(Operands);
1198    else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1199      ResTy = parseBDXAddr64(Operands);
1200    else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1201      ResTy = parseBDAddr64(Operands);
1202    else if (Kind == MCK_PCRel32)
1203      ResTy = parsePCRel32(Operands);
1204    else if (Kind == MCK_PCRel16)
1205      ResTy = parsePCRel16(Operands);
1206    else {
1207      // Only remaining operand kind is an immediate.
1208      const MCExpr *Expr;
1209      SMLoc StartLoc = Parser.getTok().getLoc();
1210
1211      // Expect immediate expression.
1212      if (Parser.parseExpression(Expr))
1213        return Error(StartLoc, "unexpected token in directive");
1214
1215      SMLoc EndLoc =
1216        SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1217
1218      Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1219      ResTy = MatchOperand_Success;
1220    }
1221
1222    if (ResTy != MatchOperand_Success)
1223      return true;
1224  }
1225
1226  // Build the instruction with the parsed operands.
1227  MCInst Inst = MCInstBuilder(Entry->Opcode);
1228
1229  for (size_t i = 0; i < Operands.size(); i++) {
1230    MCParsedAsmOperand &Operand = *Operands[i];
1231    MatchClassKind Kind = Entry->OperandKinds[i];
1232
1233    // Verify operand.
1234    unsigned Res = validateOperandClass(Operand, Kind);
1235    if (Res != Match_Success)
1236      return Error(Operand.getStartLoc(), "unexpected operand type");
1237
1238    // Add operands to instruction.
1239    SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1240    if (ZOperand.isReg())
1241      ZOperand.addRegOperands(Inst, 1);
1242    else if (ZOperand.isMem(BDMem))
1243      ZOperand.addBDAddrOperands(Inst, 2);
1244    else if (ZOperand.isMem(BDXMem))
1245      ZOperand.addBDXAddrOperands(Inst, 3);
1246    else if (ZOperand.isImm())
1247      ZOperand.addImmOperands(Inst, 1);
1248    else
1249      llvm_unreachable("unexpected operand type");
1250  }
1251
1252  // Emit as a regular instruction.
1253  Parser.getStreamer().emitInstruction(Inst, getSTI());
1254
1255  return false;
1256}
1257
1258bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1259                                     SMLoc &EndLoc, bool RestoreOnFailure) {
1260  Register Reg;
1261  if (parseRegister(Reg, RestoreOnFailure))
1262    return true;
1263  if (Reg.Group == RegGR)
1264    RegNo = SystemZMC::GR64Regs[Reg.Num];
1265  else if (Reg.Group == RegFP)
1266    RegNo = SystemZMC::FP64Regs[Reg.Num];
1267  else if (Reg.Group == RegV)
1268    RegNo = SystemZMC::VR128Regs[Reg.Num];
1269  else if (Reg.Group == RegAR)
1270    RegNo = SystemZMC::AR32Regs[Reg.Num];
1271  else if (Reg.Group == RegCR)
1272    RegNo = SystemZMC::CR64Regs[Reg.Num];
1273  StartLoc = Reg.StartLoc;
1274  EndLoc = Reg.EndLoc;
1275  return false;
1276}
1277
1278bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1279                                     SMLoc &EndLoc) {
1280  return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1281}
1282
1283OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1284                                                        SMLoc &StartLoc,
1285                                                        SMLoc &EndLoc) {
1286  bool Result =
1287      ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1288  bool PendingErrors = getParser().hasPendingError();
1289  getParser().clearPendingErrors();
1290  if (PendingErrors)
1291    return MatchOperand_ParseFail;
1292  if (Result)
1293    return MatchOperand_NoMatch;
1294  return MatchOperand_Success;
1295}
1296
1297bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1298                                        StringRef Name, SMLoc NameLoc,
1299                                        OperandVector &Operands) {
1300  Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1301
1302  // Read the remaining operands.
1303  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1304    // Read the first operand.
1305    if (parseOperand(Operands, Name)) {
1306      return true;
1307    }
1308
1309    // Read any subsequent operands.
1310    while (getLexer().is(AsmToken::Comma)) {
1311      Parser.Lex();
1312      if (parseOperand(Operands, Name)) {
1313        return true;
1314      }
1315    }
1316    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1317      SMLoc Loc = getLexer().getLoc();
1318      return Error(Loc, "unexpected token in argument list");
1319    }
1320  }
1321
1322  // Consume the EndOfStatement.
1323  Parser.Lex();
1324  return false;
1325}
1326
1327bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1328                                    StringRef Mnemonic) {
1329  // Check if the current operand has a custom associated parser, if so, try to
1330  // custom parse the operand, or fallback to the general approach.  Force all
1331  // features to be available during the operand check, or else we will fail to
1332  // find the custom parser, and then we will later get an InvalidOperand error
1333  // instead of a MissingFeature errror.
1334  FeatureBitset AvailableFeatures = getAvailableFeatures();
1335  FeatureBitset All;
1336  All.set();
1337  setAvailableFeatures(All);
1338  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1339  setAvailableFeatures(AvailableFeatures);
1340  if (ResTy == MatchOperand_Success)
1341    return false;
1342
1343  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1344  // there was a match, but an error occurred, in which case, just return that
1345  // the operand parsing failed.
1346  if (ResTy == MatchOperand_ParseFail)
1347    return true;
1348
1349  // Check for a register.  All real register operands should have used
1350  // a context-dependent parse routine, which gives the required register
1351  // class.  The code is here to mop up other cases, like those where
1352  // the instruction isn't recognized.
1353  if (Parser.getTok().is(AsmToken::Percent)) {
1354    Register Reg;
1355    if (parseRegister(Reg))
1356      return true;
1357    Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1358    return false;
1359  }
1360
1361  // The only other type of operand is an immediate or address.  As above,
1362  // real address operands should have used a context-dependent parse routine,
1363  // so we treat any plain expression as an immediate.
1364  SMLoc StartLoc = Parser.getTok().getLoc();
1365  Register Reg1, Reg2;
1366  bool HaveReg1, HaveReg2;
1367  const MCExpr *Expr;
1368  const MCExpr *Length;
1369  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1370                   /*HasLength*/ true, /*HasVectorIndex*/ true))
1371    return true;
1372  // If the register combination is not valid for any instruction, reject it.
1373  // Otherwise, fall back to reporting an unrecognized instruction.
1374  if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1375      && parseAddressRegister(Reg1))
1376    return true;
1377  if (HaveReg2 && parseAddressRegister(Reg2))
1378    return true;
1379
1380  SMLoc EndLoc =
1381    SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1382  if (HaveReg1 || HaveReg2 || Length)
1383    Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1384  else
1385    Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1386  return false;
1387}
1388
1389static std::string SystemZMnemonicSpellCheck(StringRef S,
1390                                             const FeatureBitset &FBS,
1391                                             unsigned VariantID = 0);
1392
1393bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1394                                               OperandVector &Operands,
1395                                               MCStreamer &Out,
1396                                               uint64_t &ErrorInfo,
1397                                               bool MatchingInlineAsm) {
1398  MCInst Inst;
1399  unsigned MatchResult;
1400
1401  FeatureBitset MissingFeatures;
1402  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1403                                     MissingFeatures, MatchingInlineAsm);
1404  switch (MatchResult) {
1405  case Match_Success:
1406    Inst.setLoc(IDLoc);
1407    Out.emitInstruction(Inst, getSTI());
1408    return false;
1409
1410  case Match_MissingFeature: {
1411    assert(MissingFeatures.any() && "Unknown missing feature!");
1412    // Special case the error message for the very common case where only
1413    // a single subtarget feature is missing
1414    std::string Msg = "instruction requires:";
1415    for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1416      if (MissingFeatures[I]) {
1417        Msg += " ";
1418        Msg += getSubtargetFeatureName(I);
1419      }
1420    }
1421    return Error(IDLoc, Msg);
1422  }
1423
1424  case Match_InvalidOperand: {
1425    SMLoc ErrorLoc = IDLoc;
1426    if (ErrorInfo != ~0ULL) {
1427      if (ErrorInfo >= Operands.size())
1428        return Error(IDLoc, "too few operands for instruction");
1429
1430      ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1431      if (ErrorLoc == SMLoc())
1432        ErrorLoc = IDLoc;
1433    }
1434    return Error(ErrorLoc, "invalid operand for instruction");
1435  }
1436
1437  case Match_MnemonicFail: {
1438    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1439    std::string Suggestion = SystemZMnemonicSpellCheck(
1440      ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1441    return Error(IDLoc, "invalid instruction" + Suggestion,
1442                 ((SystemZOperand &)*Operands[0]).getLocRange());
1443  }
1444  }
1445
1446  llvm_unreachable("Unexpected match type");
1447}
1448
1449OperandMatchResultTy
1450SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1451                             int64_t MaxVal, bool AllowTLS) {
1452  MCContext &Ctx = getContext();
1453  MCStreamer &Out = getStreamer();
1454  const MCExpr *Expr;
1455  SMLoc StartLoc = Parser.getTok().getLoc();
1456  if (getParser().parseExpression(Expr))
1457    return MatchOperand_NoMatch;
1458
1459  auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1460    if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1461      int64_t Value = CE->getValue();
1462      if ((Value & 1) || Value < MinVal || Value > MaxVal)
1463        return true;
1464    }
1465    return false;
1466  };
1467
1468  // For consistency with the GNU assembler, treat immediates as offsets
1469  // from ".".
1470  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1471    if (isOutOfRangeConstant(CE)) {
1472      Error(StartLoc, "offset out of range");
1473      return MatchOperand_ParseFail;
1474    }
1475    int64_t Value = CE->getValue();
1476    MCSymbol *Sym = Ctx.createTempSymbol();
1477    Out.emitLabel(Sym);
1478    const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1479                                                 Ctx);
1480    Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1481  }
1482
1483  // For consistency with the GNU assembler, conservatively assume that a
1484  // constant offset must by itself be within the given size range.
1485  if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1486    if (isOutOfRangeConstant(BE->getLHS()) ||
1487        isOutOfRangeConstant(BE->getRHS())) {
1488      Error(StartLoc, "offset out of range");
1489      return MatchOperand_ParseFail;
1490    }
1491
1492  // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1493  const MCExpr *Sym = nullptr;
1494  if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1495    Parser.Lex();
1496
1497    if (Parser.getTok().isNot(AsmToken::Identifier)) {
1498      Error(Parser.getTok().getLoc(), "unexpected token");
1499      return MatchOperand_ParseFail;
1500    }
1501
1502    MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1503    StringRef Name = Parser.getTok().getString();
1504    if (Name == "tls_gdcall")
1505      Kind = MCSymbolRefExpr::VK_TLSGD;
1506    else if (Name == "tls_ldcall")
1507      Kind = MCSymbolRefExpr::VK_TLSLDM;
1508    else {
1509      Error(Parser.getTok().getLoc(), "unknown TLS tag");
1510      return MatchOperand_ParseFail;
1511    }
1512    Parser.Lex();
1513
1514    if (Parser.getTok().isNot(AsmToken::Colon)) {
1515      Error(Parser.getTok().getLoc(), "unexpected token");
1516      return MatchOperand_ParseFail;
1517    }
1518    Parser.Lex();
1519
1520    if (Parser.getTok().isNot(AsmToken::Identifier)) {
1521      Error(Parser.getTok().getLoc(), "unexpected token");
1522      return MatchOperand_ParseFail;
1523    }
1524
1525    StringRef Identifier = Parser.getTok().getString();
1526    Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1527                                  Kind, Ctx);
1528    Parser.Lex();
1529  }
1530
1531  SMLoc EndLoc =
1532    SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1533
1534  if (AllowTLS)
1535    Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1536                                                    StartLoc, EndLoc));
1537  else
1538    Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1539
1540  return MatchOperand_Success;
1541}
1542
1543// Force static initialization.
1544extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1545  RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1546}
1547