Searched refs:MIB (Results 1 - 25 of 134) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrBuilder.h32 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument
35 return MIB.addImm(Offset).addFrameIndex(FI);
37 return MIB.addFrameIndex(FI).addImm(Offset);
/freebsd-13-stable/share/snmp/mibs/
H A DMakefile3 FILES= FREEBSD-MIB.txt
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_bridge/
H A DMakefile14 BMIBS= BRIDGE-MIB.txt BEGEMOT-BRIDGE-MIB.txt RSTP-MIB.txt
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
157 addRegOffset(const MachineInstrBuilder &MIB, argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument
167 return MIB
172 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument
198 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument
223 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument
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H A DX86CallLowering.cpp100 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
124 MIB.addUse(PhysReg, RegState::Implicit);
139 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); variable
140 ExtReg = MIB.getReg(0);
178 MachineInstrBuilder &MIB; member in struct:__anon4415::OutgoingValueHandler
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); local
218 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
223 MIRBuilder.insertInstr(MIB);
99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB, CCAssignFn *AssignFn) argument
313 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn, MachineInstrBuilder &MIB) argument
322 MachineInstrBuilder &MIB; member in struct:__anon4416::CallReturnHandler
403 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc) local
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H A DX86FixupBWInsts.cpp298 MachineInstrBuilder MIB =
303 MIB.add(MI->getOperand(i));
305 MIB.setMemRefs(MI->memoperands());
307 return MIB;
333 MachineInstrBuilder MIB =
341 MIB.add(Op);
343 return MIB;
361 MachineInstrBuilder MIB =
366 MIB.add(MI->getOperand(i));
368 MIB
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
233 static bool selectMergeValues(MachineInstrBuilder &MIB, argument
242 Register VReg0 = MIB.getReg(0);
247 Register VReg1 = MIB.getReg(1);
252 Register VReg2 = MIB.getReg(2);
258 MIB->setDesc(TII.get(ARM::VMOVDRR));
259 MIB
264 selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
485 InsertInfo(MachineInstrBuilder &MIB) argument
528 selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const argument
611 selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const argument
769 selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const argument
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H A DARMExpandPseudoInsts.cpp510 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
529 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
533 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
535 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
537 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
539 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
543 MIB.add(MI.getOperand(OpIdx++));
546 MIB.add(MI.getOperand(OpIdx++));
547 MIB.add(MI.getOperand(OpIdx++));
571 MIB
621 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
698 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
783 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); local
1568 MachineInstrBuilder MIB = local
1581 MachineInstrBuilder MIB; local
1649 addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI) argument
1698 MachineInstrBuilder MIB; local
1883 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); local
2204 MachineInstrBuilder MIB = local
2219 MachineInstrBuilder MIB; local
2315 MachineInstrBuilder MIB = local
2323 MachineInstrBuilder MIB = local
2386 MachineInstrBuilder MIB = local
2399 MachineInstrBuilder MIB = local
2430 MachineInstrBuilder MIB = local
2740 MachineInstrBuilder MIB; local
2769 MachineInstrBuilder MIB = local
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H A DThumb2SizeReduction.cpp480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) local
488 MIB.setMemRefs(MI->memoperands());
491 MIB.setMIFlags(MI->getFlags());
592 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); local
597 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
600 MIB.add(MI->getOperand(0));
601 MIB.add(MI->getOperand(1));
604 MIB.addImm(OffsetImm / Scale);
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
615 MIB
624 << " to 16-bit: " << *MIB); local
672 << " to 16-bit: " << *MIB); local
833 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
852 << " to 16-bit: " << *MIB); local
925 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
975 << " to 16-bit: " << *MIB); local
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H A DARMCallLowering.cpp90 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
122 MIB.addUse(PhysReg, RegState::Implicit);
184 MachineInstrBuilder &MIB; member in struct:__anon4009::OutgoingValueHandler
474 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
475 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
478 MIB.addDef(PhysReg, RegState::Implicit);
481 MachineInstrBuilder MIB; member in struct:__anon4010::__anon4011::CallReturnHandler
89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB, CCAssignFn *AssignFn) argument
473 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn) argument
522 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); local
[all...]
H A DThumbRegisterInfo.cpp171 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
173 MIB = MIB.add(t1CondCodeOp());
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
178 MIB.add(predOps(ARMCC::AL));
311 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
313 MIB = MIB.add(t1CondCodeOp());
314 MIB
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H A DARMLowOverheadLoops.cpp1153 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), local
1155 MIB.add(MI->getOperand(0));
1156 MIB.addImm(0);
1157 MIB.addImm(ARMCC::AL);
1158 MIB.addReg(ARM::NoRegister);
1164 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
1165 MIB.add(MI->getOperand(1)); // branch target
1166 MIB.addImm(ARMCC::EQ); // condition code
1167 MIB.addReg(ARM::CPSR);
1185 MachineInstrBuilder MIB local
1210 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), local
1223 MachineInstrBuilder MIB = local
1334 MachineInstrBuilder MIB = local
1457 MachineInstrBuilder MIB = BuildMI(*InsertAt->getParent(), InsertAt, local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h23 /// Add a BDX memory reference for frame object FI to MIB.
25 addFrameReference(const MachineInstrBuilder &MIB, int FI) { argument
26 MachineInstr *MI = MIB;
39 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_lm75/
H A DMakefile10 BMIBS= BEGEMOT-LM75-MIB.txt
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_pf/
H A DMakefile10 BMIBS= BEGEMOT-PF-MIB.txt
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_wlan/
H A DMakefile10 BMIBS= BEGEMOT-WIRELESS-MIB.txt
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp192 MachineInstrBuilder &MIB,
228 MIB.addReg(VRBase, RegState::Define);
241 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
296 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, argument
308 const MCInstrDesc &MCID = MIB->getDesc();
350 unsigned Idx = MIB->getNumOperands();
352 MIB->getOperand(Idx-1).isReg() &&
353 MIB->getOperand(Idx-1).isImplicit())
360 MIB
191 CreateVirtualRegisters(SDNode *Node, MachineInstrBuilder &MIB, const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap<SDValue, Register> &VRBaseMap) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp105 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, argument
107 assert(canPerformCSEForOpc(MIB->getOpcode()) &&
109 MachineInstr *MIBInstr = MIB;
111 return MIB;
126 MachineInstrBuilder &MIB) {
128 "Impossible return a single MIB with copies to multiple defs");
132 return buildCopy(Op.getReg(), MIB.getReg(0));
134 return MIB;
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
186 getCSEInfo()->handleRemoveInst(&*MIB);
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H A DMachineIRBuilder.cpp41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); local
42 return MIB;
45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { argument
46 getMBB().insert(getInsertPt(), MIB); local
47 recordInsertion(MIB);
48 return MIB;
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); local
103 MIB.addCImm(CI);
105 MIB.addImm(CI->getZExtValue());
107 MIB
121 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); local
130 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); local
131 Res.addDefToMIB(*getMRI(), MIB); local
140 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); local
141 Res.addDefToMIB(*getMRI(), MIB); local
153 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); local
154 Res.addDefToMIB(*getMRI(), MIB); local
335 auto MIB = buildInstr(Opcode); local
336 Res.addDefToMIB(*getMRI(), MIB); local
365 auto MIB = buildInstr(TargetOpcode::G_STORE); local
634 auto MIB = local
646 auto MIB = local
650 Result.addDefToMIB(*getMRI(), MIB); local
771 auto MIB = buildInstr(Opcode); local
772 OldValRes.addDefToMIB(*getMRI(), MIB); local
1144 auto MIB = buildInstr(Opc); local
1146 Op.addDefToMIB(*getMRI(), MIB); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.h245 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
248 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
251 void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI, argument
253 renderTruncTImm(MIB, MI, OpIdx);
256 void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI, argument
258 renderTruncTImm(MIB, MI, OpIdx);
261 void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI, argument
263 renderTruncTImm(MIB, MI, OpIdx);
266 void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, argument
268 renderTruncTImm(MIB, M
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H A DAMDGPUInstructionSelector.cpp559 MachineInstrBuilder MIB = local
563 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
564 MIB.addImm(SubRegs[I]);
693 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) local
698 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
848 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) local
855 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1267 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID))); local
1271 MIB.addReg(VSrc);
1276 MIB
1536 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode)) local
[all...]
/freebsd-13-stable/usr.sbin/bsnmpd/modules/snmp_mibII/
H A DMakefile21 BMIBS= BEGEMOT-IP-MIB.txt BEGEMOT-MIB2-MIB.txt
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp492 MachineInstrBuilder MIB; local
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
499 MIB.add(OldMI->getOperand(0));
500 MIB.add(OldMI->getOperand(2));
501 MIB.add(OldMI->getOperand(3));
502 MIB.add(ImmOp);
509 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
521 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
526 MIB
553 MachineInstrBuilder MIB; local
638 MachineInstrBuilder MIB = local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp124 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
125 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
128 MIB.addDef(PhysReg, RegState::Implicit);
131 MachineInstrBuilder MIB; member in struct:__anon3883::CallReturnHandler
136 MachineInstrBuilder MIB, CCAssignFn *AssignFn,
139 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
172 MIB.addUse(PhysReg, RegState::Implicit);
221 MachineInstrBuilder MIB; member in struct:__anon3883::OutgoingArgHandler
123 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn) argument
135 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn, CCAssignFn *AssignFnVarArg, bool IsTailCall = false, int FPDiff = 0) argument
280 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCSEMIRBuilder.h78 MachineInstrBuilder memoizeMI(MachineInstrBuilder MIB, void *NodeInsertPos);
83 MachineInstrBuilder &MIB);
86 // check if we can generate copies. It's not possible to return a single MIB,

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