Lines Matching refs:MIB
510 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
529 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
533 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
535 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
537 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
539 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
543 MIB.add(MI.getOperand(OpIdx++));
546 MIB.add(MI.getOperand(OpIdx++));
547 MIB.add(MI.getOperand(OpIdx++));
571 MIB.add(AM6Offset);
589 MIB.add(MI.getOperand(OpIdx++));
590 MIB.add(MI.getOperand(OpIdx++));
597 MIB.add(MO);
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
601 TransferImpOps(MI, MIB, MIB);
604 MIB.cloneMemRefs(MI);
606 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
621 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
625 MIB.add(MI.getOperand(OpIdx++));
628 MIB.add(MI.getOperand(OpIdx++));
629 MIB.add(MI.getOperand(OpIdx++));
652 MIB.add(AM6Offset);
661 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
663 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
665 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
667 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
670 MIB.add(MI.getOperand(OpIdx++));
671 MIB.add(MI.getOperand(OpIdx++));
674 MIB->addRegisterKilled(SrcReg, TRI, true);
676 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
677 TransferImpOps(MI, MIB, MIB);
680 MIB.cloneMemRefs(MI);
682 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
698 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
720 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
722 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
724 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
726 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
730 MIB.add(MI.getOperand(OpIdx++));
733 MIB.add(MI.getOperand(OpIdx++));
734 MIB.add(MI.getOperand(OpIdx++));
737 MIB.add(MI.getOperand(OpIdx++));
747 MIB.addReg(D0, SrcFlags);
749 MIB.addReg(D1, SrcFlags);
751 MIB.addReg(D2, SrcFlags);
753 MIB.addReg(D3, SrcFlags);
756 MIB.addImm(Lane);
760 MIB.add(MI.getOperand(OpIdx++));
761 MIB.add(MI.getOperand(OpIdx++));
765 MIB.add(MO);
768 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
769 TransferImpOps(MI, MIB, MIB);
771 MIB.cloneMemRefs(MI);
783 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
787 MIB.add(MI.getOperand(OpIdx++));
790 MIB.add(VdSrc);
797 MIB.addReg(D0);
801 MIB.add(VmSrc);
804 MIB.add(MI.getOperand(OpIdx++));
805 MIB.add(MI.getOperand(OpIdx++));
808 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
809 TransferImpOps(MI, MIB, MIB);
811 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
1568 MachineInstrBuilder MIB =
1572 MIB.addImm(0);
1573 MIB.add(predOps(ARMCC::AL));
1581 MachineInstrBuilder MIB;
1582 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
1583 MIB.addReg(AddrReg);
1585 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
1586 MIB.add(predOps(ARMCC::AL));
1605 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
1609 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
1610 MIB.add(predOps(ARMCC::AL));
1649 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1655 MIB.addReg(RegLo, Flags);
1656 MIB.addReg(RegHi, Flags);
1658 MIB.addReg(Reg.getReg(), Flags);
1698 MachineInstrBuilder MIB;
1699 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1700 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1701 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1727 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1729 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
1730 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1883 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1885 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1889 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1895 MIB.add(predOps(ARMCC::AL));
2204 MachineInstrBuilder MIB =
2211 TransferImpOps(MI, MIB, MIB);
2219 MachineInstrBuilder MIB;
2228 MIB =
2233 MIB.addImm(0);
2234 MIB.add(predOps(ARMCC::AL));
2236 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2239 MIB.add(predOps(ARMCC::AL));
2240 MIB.addReg(Reg, RegState::Kill);
2242 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2245 MIB.add(predOps(ARMCC::AL));
2246 MIB.addExternalSymbol("__aeabi_read_tp", 0);
2249 MIB.cloneMemRefs(MI);
2250 TransferImpOps(MI, MIB, MIB);
2253 MF->moveCallSiteInfo(&MI, &*MIB);
2315 MachineInstrBuilder MIB =
2319 MIB.addImm(0);
2320 MIB.add(predOps(ARMCC::AL));
2323 MachineInstrBuilder MIB =
2330 MIB.add(predOps(ARMCC::AL));
2386 MachineInstrBuilder MIB =
2393 TransferImpOps(MI, MIB, MIB);
2399 MachineInstrBuilder MIB =
2408 MIB.add(MI.getOperand(OpIdx++));
2411 MIB.add(MI.getOperand(OpIdx++));
2412 MIB.add(MI.getOperand(OpIdx++));
2417 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
2421 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
2422 TransferImpOps(MI, MIB, MIB);
2423 MIB.cloneMemRefs(MI);
2430 MachineInstrBuilder MIB =
2440 MIB.add(Dst);
2443 MIB.add(MI.getOperand(OpIdx++));
2444 MIB.add(MI.getOperand(OpIdx++));
2449 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
2453 MIB->addRegisterKilled(SrcReg, TRI, true);
2455 TransferImpOps(MI, MIB, MIB);
2456 MIB.cloneMemRefs(MI);
2740 MachineInstrBuilder MIB;
2748 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
2758 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
2760 MIB.cloneMemRefs(MI);
2761 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i));
2769 MachineInstrBuilder MIB =
2777 MIB.add(MI.getOperand(i));
2778 MIB.add(predOps(ARMCC::AL));
2779 MIB.cloneMemRefs(MI);