Lines Matching refs:MIB
559 MachineInstrBuilder MIB =
563 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
564 MIB.addImm(SubRegs[I]);
693 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
698 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
848 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
855 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1267 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID)));
1271 MIB.addReg(VSrc);
1276 MIB.addImm(ImmOffset)
1536 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode))
1547 MIB.addDef(TmpReg);
1552 MIB.addDef(VDataOut); // vdata output
1557 MIB.addReg(VDataIn); // vdata input
1563 MIB.addReg(SrcOp.getReg());
1567 MIB.addReg(MI.getOperand(VAddrIdx + NumVAddr).getReg()); // rsrc
1569 MIB.addReg(MI.getOperand(VAddrIdx + NumVAddr + 1).getReg()); // sampler
1571 MIB.addImm(DMask); // dmask
1574 MIB.addImm(DimInfo->Encoding);
1575 MIB.addImm(Unorm);
1577 MIB.addImm(DLC);
1579 MIB.addImm(GLC);
1580 MIB.addImm(SLC);
1581 MIB.addImm(IsA16 && // a16 or r128
1584 MIB.addImm(IsA16 ? -1 : 0);
1586 MIB.addImm(TFE); // tfe
1587 MIB.addImm(LWE); // lwe
1589 MIB.addImm(DimInfo->DA ? -1 : 0);
1591 MIB.addImm(IsD16 ? -1 : 0);
1594 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
2232 auto MIB = BuildMI(*BB, &MI, DL, TII.get(Opcode), TmpReg)
2236 MIB.addReg(VAddr);
2238 MIB.addReg(RSrcReg);
2240 MIB.addReg(SOffset);
2242 MIB.addImm(0);
2244 MIB.addImm(Offset);
2245 MIB.addImm(0); // slc
2246 MIB.cloneMemRefs(MI);
2255 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
2882 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
2928 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
2939 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
2940 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
2941 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
2942 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
2949 [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
2950 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
2951 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
2962 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
2963 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
2975 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
3012 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
3013 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3026 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
3027 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3035 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
3036 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods
3056 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
3057 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
3077 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
3078 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
3109 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
3110 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
3120 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
3121 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // offset
3122 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // slc
3144 [=](MachineInstrBuilder &MIB) { MIB.addReg(BasePtr); },
3145 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset.getValue()); },
3146 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // slc
3183 return {{[=](MachineInstrBuilder &MIB) { // rsrc
3184 MIB.addReg(Info->getScratchRSrcReg());
3186 [=](MachineInstrBuilder &MIB) { // vaddr
3187 MIB.addReg(HighBits);
3189 [=](MachineInstrBuilder &MIB) { // soffset
3194 MIB.addReg(Info->getStackPtrOffsetReg());
3196 MIB.addImm(0);
3198 [=](MachineInstrBuilder &MIB) { // offset
3199 MIB.addImm(Offset & 4095);
3233 return {{[=](MachineInstrBuilder &MIB) { // rsrc
3234 MIB.addReg(Info->getScratchRSrcReg());
3236 [=](MachineInstrBuilder &MIB) { // vaddr
3238 MIB.addFrameIndex(FI.getValue());
3240 MIB.addReg(VAddr);
3242 [=](MachineInstrBuilder &MIB) { // soffset
3249 MIB.addReg(Info->getStackPtrOffsetReg());
3251 MIB.addImm(0);
3253 [=](MachineInstrBuilder &MIB) { // offset
3254 MIB.addImm(Offset);
3290 [=](MachineInstrBuilder &MIB) { // rsrc
3291 MIB.addReg(Info->getScratchRSrcReg());
3293 [=](MachineInstrBuilder &MIB) { // soffset
3295 MIB.addReg(Info->getStackPtrOffsetReg());
3297 MIB.addImm(0);
3299 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset
3339 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
3340 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }
3350 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
3351 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); },
3352 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); }
3406 static void addZeroImm(MachineInstrBuilder &MIB) {
3407 MIB.addImm(0);
3615 [=](MachineInstrBuilder &MIB) { // rsrc
3616 MIB.addReg(RSrcReg);
3618 [=](MachineInstrBuilder &MIB) { // vaddr
3619 MIB.addReg(VAddr);
3621 [=](MachineInstrBuilder &MIB) { // soffset
3623 MIB.addReg(SOffset);
3625 MIB.addImm(0);
3627 [=](MachineInstrBuilder &MIB) { // offset
3628 MIB.addImm(Offset);
3648 [=](MachineInstrBuilder &MIB) { // rsrc
3649 MIB.addReg(RSrcReg);
3651 [=](MachineInstrBuilder &MIB) { // soffset
3653 MIB.addReg(SOffset);
3655 MIB.addImm(0);
3657 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset
3679 [=](MachineInstrBuilder &MIB) { // rsrc
3680 MIB.addReg(RSrcReg);
3682 [=](MachineInstrBuilder &MIB) { // vaddr
3683 MIB.addReg(VAddr);
3685 [=](MachineInstrBuilder &MIB) { // soffset
3687 MIB.addReg(SOffset);
3689 MIB.addImm(0);
3691 [=](MachineInstrBuilder &MIB) { // offset
3692 MIB.addImm(Offset);
3708 [=](MachineInstrBuilder &MIB) { // rsrc
3709 MIB.addReg(RSrcReg);
3711 [=](MachineInstrBuilder &MIB) { // soffset
3713 MIB.addReg(SOffset);
3715 MIB.addImm(0);
3717 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset
3743 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }};
3759 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }};
3762 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB,
3767 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue());
3770 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB,
3775 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue());
3778 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB,
3785 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
3788 MIB.addImm(Op.getCImm()->getSExtValue());
3792 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
3797 MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation());
3802 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB,
3805 MIB.addImm(MI.getOperand(OpIdx).getImm());
3808 void AMDGPUInstructionSelector::renderExtractGLC(MachineInstrBuilder &MIB,
3812 MIB.addImm(MI.getOperand(OpIdx).getImm() & 1);
3815 void AMDGPUInstructionSelector::renderExtractSLC(MachineInstrBuilder &MIB,
3819 MIB.addImm((MI.getOperand(OpIdx).getImm() >> 1) & 1);
3822 void AMDGPUInstructionSelector::renderExtractDLC(MachineInstrBuilder &MIB,
3826 MIB.addImm((MI.getOperand(OpIdx).getImm() >> 2) & 1);
3829 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB,
3833 MIB.addImm((MI.getOperand(OpIdx).getImm() >> 3) & 1);