/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 33 : ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II), 40 if (ItinData && !ItinData->isEmpty()) { 42 if (ItinData->isEndMarker(idx)) 45 const InstrStage *IS = ItinData->beginStage(idx); 46 const InstrStage *E = ItinData->endStage(idx); 74 IssueWidth = ItinData->SchedModel.IssueWidth; 114 if (!ItinData || ItinData->isEmpty()) 129 for (const InstrStage *IS = ItinData [all...] |
H A D | TargetInstrInfo.cpp | 1062 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, argument 1065 if (!ItinData || ItinData->isEmpty()) 1073 return ItinData->getOperandCycle(DefClass, DefIdx); 1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 1078 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, argument 1080 if (!ItinData || ItinData->isEmpty()) 1086 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); 1093 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, argument 1124 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost) const argument 1138 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); local 1230 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument 1242 computeDefOperandLatency( const InstrItineraryData *ItinData, const MachineInstr &DefMI) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.h | 34 ARMHazardRecognizer(const InstrItineraryData *ItinData, argument 36 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched") {}
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H A D | ARMBaseInstrInfo.h | 327 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 330 int getOperandLatency(const InstrItineraryData *ItinData, 334 int getOperandLatency(const InstrItineraryData *ItinData, 382 int getVLDMDefCycle(const InstrItineraryData *ItinData, 386 int getLDMDefCycle(const InstrItineraryData *ItinData, 390 int getVSTMUseCycle(const InstrItineraryData *ItinData, 394 int getSTMUseCycle(const InstrItineraryData *ItinData, 398 int getOperandLatency(const InstrItineraryData *ItinData, 404 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 413 unsigned getInstrLatency(const InstrItineraryData *ItinData, [all...] |
H A D | ARMBaseInstrInfo.cpp | 3387 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, argument 3392 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 3689 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, argument 3691 if (!ItinData || ItinData->isEmpty()) 3696 int ItinUOps = ItinData->getNumMicroOps(Class); 3699 return getNumMicroOpsSwiftLdSt(ItinData, MI); 3803 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, argument 3810 return ItinData->getOperandCycle(DefClass, DefIdx); 3860 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, argument 3895 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3935 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3964 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 4308 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument 4344 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument 4405 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 4682 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost) const argument 4733 getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const argument 4775 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, argument 36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
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H A D | PPCInstrInfo.h | 293 unsigned getInstrLatency(const InstrItineraryData *ItinData, 297 int getOperandLatency(const InstrItineraryData *ItinData, 301 int getOperandLatency(const InstrItineraryData *ItinData, 304 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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H A D | PPCInstrInfo.cpp | 125 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, argument 128 if (!ItinData || UseOldLatencyCalc) 129 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); 145 int Cycle = ItinData->getOperandCycle(DefClass, i); 155 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, argument 159 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, 181 Latency = getInstrLatency(ItinData, DefMI);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ScoreboardHazardRecognizer.h | 94 const InstrItineraryData *ItinData; member in class:llvm::ScoreboardHazardRecognizer
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H A D | TargetInstrInfo.h | 1465 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1476 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1488 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1496 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1502 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1509 int computeDefOperandLatency(const InstrItineraryData *ItinData,
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/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | SubtargetEmitter.cpp | 82 Record *ItinData, std::string &ItinString, 84 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString, 87 Record *ItinData, 295 Record *ItinData, 299 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); 338 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, argument 342 ItinData->getValueAsListOfInts("OperandCycles"); 356 Record *ItinData, 359 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); 457 Record *ItinData local 294 FormItineraryStageString(const std::string &Name, Record *ItinData, std::string &ItinString, unsigned &NStages) argument 355 FormItineraryBypassString(const std::string &Name, Record *ItinData, std::string &ItinString, unsigned NOperandCycles) argument 463 FormItineraryStageString(std::string(Name), ItinData, ItinStageString, local 474 FormItineraryBypassString(std::string(Name), ItinData, ItinBypassString, local [all...] |
H A D | CodeGenSchedule.cpp | 1164 for (Record *ItinData : ItinRecords) { 1165 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); 1172 ProcModel.ItinDefList[SC.Index] = ItinData;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 278 unsigned getInstrLatency(const InstrItineraryData *ItinData, 310 int getOperandLatency(const InstrItineraryData *ItinData, 454 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
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H A D | HexagonInstrInfo.cpp | 1881 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, argument 1884 return getInstrTimingClassLatency(ItinData, MI); 4198 const InstrItineraryData *ItinData, const MachineInstr &MI) const { 4201 if (!ItinData) 4202 return getInstrLatency(ItinData, MI); 4206 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); 4217 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, argument 4250 int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, 4197 getInstrTimingClassLatency( const InstrItineraryData *ItinData, const MachineInstr &MI) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 208 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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H A D | SIInstrInfo.h | 1053 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A D | R600InstrInfo.cpp | 1009 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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H A D | SIInstrInfo.cpp | 7145 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, argument
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