Lines Matching refs:ItinData
1062 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1065 if (!ItinData || ItinData->isEmpty())
1073 return ItinData->getOperandCycle(DefClass, DefIdx);
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1078 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1080 if (!ItinData || ItinData->isEmpty())
1086 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1093 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1095 if (!ItinData || ItinData->isEmpty())
1099 int UOps = ItinData->Itineraries[Class].NumMicroOps;
1124 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1129 if (!ItinData)
1132 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1138 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1139 if (!ItinData || ItinData->isEmpty())
1143 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1230 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1237 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1243 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const {
1246 if (!ItinData)
1247 return getInstrLatency(ItinData, DefMI);
1249 if(ItinData->isEmpty())
1250 return defaultDefLatency(ItinData->SchedModel, DefMI);