Lines Matching refs:ItinData
3387 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3392 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3689 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3691 if (!ItinData || ItinData->isEmpty())
3696 int ItinUOps = ItinData->getNumMicroOps(Class);
3699 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3803 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3810 return ItinData->getOperandCycle(DefClass, DefIdx);
3860 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3867 return ItinData->getOperandCycle(DefClass, DefIdx);
3895 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3901 return ItinData->getOperandCycle(UseClass, UseIdx);
3935 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3941 return ItinData->getOperandCycle(UseClass, UseIdx);
3964 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3973 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3982 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3991 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4012 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4023 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4032 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4050 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4063 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4066 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4308 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4314 if (!ItinData || ItinData->isEmpty())
4340 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4345 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4360 unsigned Latency = getInstrLatency(ItinData, DefMI);
4386 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
4405 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4416 if (!ItinData || ItinData->isEmpty())
4420 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4435 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
4682 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4697 Latency += getInstrLatency(ItinData, *I, PredCost);
4711 if (!ItinData)
4717 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4718 return getNumMicroOps(ItinData, MI);
4721 unsigned Latency = ItinData->getStageLatency(Class);
4733 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4738 if (!ItinData || ItinData->isEmpty())
4744 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4775 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4776 if (!ItinData || ItinData->isEmpty())
4782 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);