/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 253 Register DefReg = Def.getReg(); local 254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 288 Register DefReg = Def.getReg(); local 289 if (!Register::isVirtualRegister(DefReg)) 291 unsigned DefRegIdx = Register::virtReg2Index(DefReg); 431 Register DefReg = Def.getReg(); local 434 if (Register::isVirtualRegister(DefReg)) { 438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); 473 Register DefReg = Def.getReg(); local 474 if (!Register::isVirtualRegister(DefReg)) [all...] |
H A D | TailDuplicator.cpp | 352 Register DefReg = MI->getOperand(0).getReg(); local 357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); 364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) 365 addSSAUpdateEntry(DefReg, NewDef, PredBB);
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H A D | ImplicitNullChecks.cpp | 631 unsigned DefReg = NoRegister; local 633 DefReg = MI->getOperand(0).getReg(); 644 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
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H A D | MachineSink.cpp | 1187 for (auto DefReg : DefedRegsInCopy) { 1189 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); 1222 for (unsigned DefReg : DefedRegsInCopy) 1223 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S) 1351 "Unexpect SrcReg or DefReg");
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H A D | PHIElimination.cpp | 203 Register DefReg = DefMI->getOperand(0).getReg(); local 204 if (MRI->use_nodbg_empty(DefReg)) {
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H A D | TargetInstrInfo.cpp | 899 Register DefReg = MI.getOperand(0).getReg(); 905 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && 906 MI.readsVirtualRegister(DefReg)) 957 if (MO.isDef() && Reg != DefReg)
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H A D | LiveVariables.cpp | 218 Register DefReg = MO.getReg(); local 219 if (TRI->isSubRegister(Reg, DefReg)) { 220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegStackify.cpp | 475 Register DefReg = MO.getReg(); 476 if (!Register::isVirtualRegister(DefReg) || 477 !MFI.isVRegStackified(DefReg)) 479 assert(MRI.hasOneNonDBGUse(DefReg)); 480 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); 624 /// DefReg = INST ... // Def (to become the new Insert) 625 /// TeeReg, Reg = TEE_... DefReg 630 /// with DefReg and TeeReg stackified. This eliminates a local.get from the 647 Register DefReg = MRI.createVirtualRegister(RegClass); local 652 .addReg(DefReg, getUndefRegStat 933 unsigned DefReg = SubsequentDef->getReg(); local [all...] |
H A D | WebAssemblyExplicitLocals.cpp | 182 for (auto DefReg : Def->defs()) { 183 if (!MFI.isVRegStackified(DefReg.getReg())) {
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H A D | WebAssemblyCFGStackify.cpp | 777 // DefReg = INST ... 778 // TeeReg, Reg = TEE_... DefReg 782 // with DefReg and TeeReg stackified but Reg not stackified. 787 // DefReg = INST ... 788 // TeeReg = COPY DefReg 789 // Reg = COPY DefReg 799 Register DefReg = MI.getOperand(2).getReg(); local 801 // Now we are not using TEE anymore, so unstackify DefReg too 802 MFI.unstackifyVReg(DefReg); 803 unsigned CopyOpc = getCopyOpcode(MRI.getRegClass(DefReg)); [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RedundantCopyElimination.cpp | 382 Register DefReg = MI->getOperand(0).getReg(); local 385 if (!MRI->isReserved(DefReg) && 389 if (KnownReg.Reg != DefReg && 390 !TRI->isSuperRegister(DefReg, KnownReg.Reg))
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H A D | AArch64LoadStoreOptimizer.cpp | 745 // a def for DefReg is reached. Returns true, iff Fn returns true for all 747 static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg, 757 bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) { 759 TRI->regsOverlap(MOP.getReg(), DefReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 379 Register DefReg = MI.getOperand(I).getReg(); local 380 UpdatedDefs.push_back(DefReg); 381 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); 612 Register DefReg = MI.getOperand(DefIdx).getReg(); local 613 Builder.buildMerge(DefReg, Regs); 614 UpdatedDefs.push_back(DefReg); 628 Register DefReg = MI.getOperand(Idx).getReg(); local 629 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); 630 UpdatedDefs.push_back(DefReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 508 const Register DefReg = I.getOperand(0).getReg(); local 509 LLT Ty = MRI.getType(DefReg); 510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); 546 addFullAddress(MIB, AM).addUse(DefReg); 568 const Register DefReg = I.getOperand(0).getReg(); local 569 LLT Ty = MRI.getType(DefReg); 621 const Register DefReg = I.getOperand(0).getReg(); local 622 LLT Ty = MRI.getType(DefReg); 640 const Register DefReg = I.getOperand(0).getReg(); local 641 LLT Ty = MRI.getType(DefReg); 862 unsigned DefReg = SrcReg; local 1372 Register DefReg = MRI.createGenericVirtualRegister(DstTy); local [all...] |
H A D | X86DomainReassignment.cpp | 596 Register DefReg = DefOp.getReg(); local 597 if (!Register::isVirtualRegister(DefReg)) { 601 visitRegister(C, DefReg, Domain, Worklist);
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H A D | X86LoadValueInjectionLoadHardening.cpp | 370 RegisterRef DefReg = DFG.getPRI().normalize(Def.Addr->getRegRef(DFG)); 371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) { 376 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) {
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H A D | X86SpeculativeLoadHardening.cpp | 1786 Register DefReg = MI.getOperand(0).getReg(); 1792 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) { 1817 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) || 1818 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 369 int DefReg = 0; local 373 DefReg = MO.getReg(); 392 if (DefReg != Reg) { 407 if (DefReg!= SpReg) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXSwapRemoval.cpp | 670 Register DefReg = MI->getOperand(0).getReg(); local 676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { 700 Register DefReg = DefMI->getOperand(0).getReg(); local 719 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { 759 Register DefReg = MI->getOperand(0).getReg(); local 761 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 170 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS, 188 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred, 1768 Register DefReg = I.getOperand(0).getReg(); 1769 LLT Ty = MRI.getType(DefReg); 1772 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); 1775 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); 1812 const Register DefReg = I.getOperand(0).getReg(); local 1813 const LLT DefTy = MRI.getType(DefReg); 1816 MRI.getRegClassOrRegBank(DefReg); 1835 return RBI.constrainGenericRegister(DefReg, *DefR 1998 const Register DefReg = I.getOperand(0).getReg(); local 2345 const Register DefReg = I.getOperand(0).getReg(); local 2389 const Register DefReg = I.getOperand(0).getReg(); local 2589 const Register DefReg = I.getOperand(0).getReg(); local 2809 const Register DefReg = I.getOperand(0).getReg(); local 3713 emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS, MachineIRBuilder &MIRBuilder) const argument 3937 emitCSetForICMP(Register DefReg, unsigned Pred, MachineIRBuilder &MIRBuilder) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 204 Register DefReg = findSinkableLocalRegDef(LocalMI); local 205 if (DefReg == 0) 208 sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap); 219 static bool isRegUsedByPhiNodes(Register DefReg, argument 222 if (P.second == DefReg) 263 Register DefReg, 270 if (FuncInfo.RegsWithFixups.count(DefReg)) 275 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); 276 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { 294 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) { 262 sinkLocalValueMaterialization(MachineInstr &LocalMI, Register DefReg, InstOrderMap &OrderMap) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 215 Register DefReg = MODef.getReg(); local 216 if (!Register::isVirtualRegister(DefReg)) {
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 586 void sinkLocalValueMaterialization(MachineInstr &LocalMI, Register DefReg,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 1041 unsigned DefReg = 0; 1048 if (DefReg != 0) 1050 DefReg = R; 1052 return DefReg;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegBankSelect.cpp | 204 for (Register DefReg : NewVRegs) 205 UnMergeBuilder.addDef(DefReg);
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