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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/

Lines Matching refs:DefReg

170   MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
188 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
1768 Register DefReg = I.getOperand(0).getReg();
1769 LLT Ty = MRI.getType(DefReg);
1772 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
1775 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
1812 const Register DefReg = I.getOperand(0).getReg();
1813 const LLT DefTy = MRI.getType(DefReg);
1816 MRI.getRegClassOrRegBank(DefReg);
1835 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
1998 const Register DefReg = I.getOperand(0).getReg();
1999 const LLT DefTy = MRI.getType(DefReg);
2001 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
2064 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()});
2066 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI);
2074 MIB.buildCopy({DefReg}, {DefGPRReg});
2076 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
2345 const Register DefReg = I.getOperand(0).getReg();
2346 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
2389 const Register DefReg = I.getOperand(0).getReg();
2390 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
2589 const Register DefReg = I.getOperand(0).getReg();
2591 const LLT DstTy = MRI.getType(DefReg);
2604 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
2636 MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})
2641 if (!RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass,
2677 {DefReg}, {SrcReg})
2682 {DefReg}, {SrcReg})
2809 const Register DefReg = I.getOperand(0).getReg();
2810 Register Def1Reg = DefReg;
2831 .addDef(DefReg)
3713 AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
3723 auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS});
3937 AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
3944 .buildInstr(AArch64::CSINCWr, {DefReg}, {Register(AArch64::WZR), Register(AArch64::WZR)})
4867 Register DefReg = MI.getOperand(0).getReg();
4868 if (MRI.hasOneNonDBGUse(DefReg) ||
4880 return all_of(MRI.use_nodbg_instructions(DefReg),