/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixVGPRCopies.cpp | 60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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H A D | SIFixupVectorISel.cpp | 189 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false)); 192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(TOCReg,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, 77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, 85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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H A D | ARMBaseInstrInfo.h | 501 MachineOperand::CreateReg(PredReg, false)}}; 507 return MachineOperand::CreateReg(CCReg, false); 514 return MachineOperand::CreateReg(ARM::CPSR,
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H A D | Thumb2InstrInfo.cpp | 524 MI.addOperand(MachineOperand::CreateReg(0, false)); 556 MI.addOperand(MachineOperand::CreateReg(0, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 219 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 226 MI.addOperand(MachineOperand::CreateReg(
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H A D | HexagonHardwareLoops.cpp | 1910 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true)); 1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false); 1936 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 179 Register CreateReg(MVT VT, bool isDivergent = false);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 804 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 852 Ops.push_back(MachineOperand::CreateReg( 963 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); 1012 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 1018 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); 1031 Ops.push_back(MachineOperand::CreateReg( 1037 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, 1065 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), 1067 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), 1084 Ops.push_back(MachineOperand::CreateReg(getRegForValu [all...] |
H A D | FunctionLoweringInfo.cpp | 367 /// CreateReg - Allocate a single virtual register for the given type. 368 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { function in class:FunctionLoweringInfo 393 Register R = CreateReg(RegisterVT, isDivergent);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, 400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
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H A D | LiveDebugVariables.cpp | 661 MachineOperand MO = MachineOperand::CreateReg(0U, false); 1067 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false); 1314 : MachineOperand::CreateReg(
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H A D | MachineOutliner.cpp | 830 MachineOperand::CreateReg(I, true, /* isDef = true */ 836 MachineOperand::CreateReg(I, false, /* isDef = false */
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H A D | MachineInstr.cpp | 107 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); 111 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); 1877 addOperand(MachineOperand::CreateReg(IncomingReg, 1944 addOperand(MachineOperand::CreateReg(Reg, 1981 addOperand(MachineOperand::CreateReg(Reg,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCOptAddrMode.cpp | 460 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); 463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
H A D | MSP430AsmParser.cpp | 199 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon4183::MSP430Operand 460 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SLSHardening.cpp | 365 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegStackify.cpp | 86 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, 92 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, 127 MI->addOperand(MachineOperand::CreateReg(TempReg, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CSEInfo.cpp | 352 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 1827 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, function in class:__anon3880::AArch64Operand 1854 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, 3471 Operands.push_back(AArch64Operand::CreateReg( 3490 Operands.push_back(AArch64Operand::CreateReg( 3507 Operands.push_back(AArch64Operand::CreateReg( 3522 Operands.push_back(AArch64Operand::CreateReg( 4614 Operands[2] = AArch64Operand::CreateReg( 4777 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, 4793 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, 4810 Operands[1] = AArch64Operand::CreateReg(Re [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
H A D | AVRAsmParser.cpp | 207 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon4067::AVROperand 397 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 2103 return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) : 2252 return X86Operand::CreateReg(Reg, Loc, EndLoc); 2366 X86Operand::CreateReg(RegNo, StartLoc, StartLoc)); 2954 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc); 2966 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), 2975 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), 2989 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), 3000 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 389 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, function in class:__anon4304::SparcOperand 841 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); 901 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
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