Searched refs:ATH_READ_REG (Results 1 - 22 of 22) sorted by relevance

/freebsd-13-stable/sys/mips/atheros/ar531x/
H A Dar5315_chip.c85 memcfg = ATH_READ_REG(AR5315_SDRAMCTL_BASE + AR5315_SDRAMCTL_MEM_CFG);
121 const uint32_t pllc = ATH_READ_REG(AR5315_SYSREG_BASE +
145 const uint32_t amba_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
151 const uint32_t cpu_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
175 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR1);
182 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) |
188 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN) |
195 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL));
197 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN));
205 reg = ATH_READ_REG(AR5315_SYSREG_BAS
[all...]
H A Dar5312_chip.c73 memcfg = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
90 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL);
125 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0);
126 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
139 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR);
140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE);
145 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) |
155 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL);
H A Dapb.c102 reg = ATH_READ_REG(AR5315_SYSREG_BASE +
107 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
121 reg = ATH_READ_REG(AR5315_SYSREG_BASE +
126 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
489 reg = ATH_READ_REG(AR5315_SYSREG_BASE +
492 reg = ATH_READ_REG(AR5312_SYSREG_BASE +
510 ATH_READ_REG(AR5312_SYSREG_BASE +
512 ATH_READ_REG(AR5312_SYSREG_BASE +
542 intr = ATH_READ_REG(AR5315_SYSREG_BASE +
545 intr = ATH_READ_REG(AR5312_SYSREG_BAS
[all...]
H A Dar5315_setup.c109 ver = ATH_READ_REG(AR5315_SYSREG_BASE +
133 ver = ATH_READ_REG(AR5312_SYSREG_BASE +
H A Dar5315reg.h224 #define ATH_READ_REG(reg) \ macro
H A Dar5315_spi.c146 *((uint32_t *)data + i) = ATH_READ_REG(AR5315_MEM1_BASE + offset + i * 4);
/freebsd-13-stable/sys/mips/atheros/
H A Dar934x_chip.c99 bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
105 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
109 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
117 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
132 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
136 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
144 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
159 clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
197 reg = ATH_READ_REG(AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
212 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODUL
[all...]
H A Dqca953x_chip.c80 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
86 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG);
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG);
114 clk_ctrl = ATH_READ_REG(QCA953X_PLL_CLK_CTRL_REG);
161 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
170 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
179 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
265 reg = ATH_READ_REG(QCA953X_GMAC_REG_ETH_CFG);
281 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
367 t = ATH_READ_REG(AR71XX_GPIO_BAS
[all...]
H A Dar933x_chip.c78 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
84 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
90 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
144 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
153 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
162 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
258 reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG);
H A Dqca955x_chip.c81 bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP);
87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
115 clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG);
162 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
171 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
180 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
278 reg = ATH_READ_REG(QCA955X_GMAC_REG_ETH_CFG);
376 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
382 ATH_READ_REG(AR71XX_GPIO_BAS
[all...]
H A Dar724x_chip.c78 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
103 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
115 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
126 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
H A Dar91xx_chip.c76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
96 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
105 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
114 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
H A Dar71xx_chip.c100 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
125 reg = ATH_READ_REG(AR71XX_RST_RESET);
134 reg = ATH_READ_REG(AR71XX_RST_RESET);
143 reg = ATH_READ_REG(AR71XX_RST_RESET);
181 val = ATH_READ_REG(reg);
227 val = ATH_READ_REG(reg);
H A Dqca955x_pci.c124 val = ATH_READ_REG(reg + (offset & ~3));
155 data = ATH_READ_REG(sc->sc_pci_reg_base + (reg & ~3));
194 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);
199 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS);
215 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);
236 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
240 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
243 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
249 (void) ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP);
253 reg = ATH_READ_REG(s
[all...]
H A Dar71xx_pci.c108 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
110 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
121 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
124 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
156 error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3;
159 addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR);
169 error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1;
172 addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR);
237 data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA);
623 reg = ATH_READ_REG(AR71XX_PCI_INTR_STATU
[all...]
H A Dar724x_pci.c110 val = ATH_READ_REG(reg + (offset & ~3));
142 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
197 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
202 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
218 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
236 reg = ATH_READ_REG(AR724X_PCI_RESET);
251 (void) ATH_READ_REG(AR724X_PCI_APP);
255 reg = ATH_READ_REG(AR724X_PCI_RESET);
263 reg = ATH_READ_REG(AR724X_PCI_APP);
597 reg = ATH_READ_REG(AR724X_PCI_INTR_STATU
[all...]
H A Dar71xxreg.h532 #define ATH_READ_REG(reg) \ macro
546 while ((ATH_READ_REG(reg) & 0x1))
549 while ((ATH_READ_REG(reg) & 0x1))
559 sec_cfg = ATH_READ_REG(cfg_reg);
H A Duart_bus_ar71xx.c98 if (ATH_READ_REG(AR71XX_UART_ADDR + AR71XX_UART_LSR)
H A Duart_bus_ar933x.c106 while ((i > 0) && (ATH_READ_REG(AR71XX_UART_ADDR + AR933X_UART_CS_REG) &
H A Dar71xx_wdog.c156 if (ATH_READ_REG(AR71XX_RST_WDOG_CONTROL) & RST_WDOG_LAST) {
H A Dapb.c91 reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK);
102 reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK);
356 reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS);
H A Dar71xx_setup.c89 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);

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