1/*- 2 * Copyright (c) 2016 Hiroki Mori 3 * Copyright (c) 2010 Adrian Chadd 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include "opt_ddb.h" 32 33#include <sys/param.h> 34#include <sys/conf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/cons.h> 40#include <sys/kdb.h> 41#include <sys/reboot.h> 42 43#include <vm/vm.h> 44#include <vm/vm_page.h> 45 46#include <net/ethernet.h> 47 48#include <machine/clock.h> 49#include <machine/cpu.h> 50#include <machine/cpuregs.h> 51#include <machine/hwfunc.h> 52#include <machine/md_var.h> 53#include <machine/trap.h> 54#include <machine/vmparam.h> 55 56#include <mips/atheros/ar531x/ar5312reg.h> 57#include <mips/atheros/ar531x/ar5315reg.h> 58#include <mips/atheros/ar531x/ar5315_cpudef.h> 59#include <mips/atheros/ar531x/ar5315_setup.h> 60 61static void 62ar5312_chip_detect_mem_size(void) 63{ 64 uint32_t memsize; 65 uint32_t memcfg, bank0, bank1; 66 67 /* 68 * Determine the memory size as established by system 69 * firmware. 70 * 71 * NB: we allow compile time override 72 */ 73 memcfg = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1); 74 bank0 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK0); 75 bank1 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK1); 76 77 memsize = (bank0 ? (1 << (bank0 + 1)) : 0) + 78 (bank1 ? (1 << (bank1 + 1)) : 0); 79 memsize <<= 20; 80 81 realmem = memsize; 82} 83 84static void 85ar5312_chip_detect_sys_frequency(void) 86{ 87 uint32_t predivisor; 88 uint32_t multiplier; 89 90 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL); 91 if(ar531x_soc == AR531X_SOC_AR5313) { 92 predivisor = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_PREDIVIDE); 93 multiplier = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_MULTIPLIER); 94 } else { 95 predivisor = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_PREDIVIDE); 96 multiplier = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_MULTIPLIER); 97 } 98 99 const uint32_t divisor = (0x5421 >> (predivisor * 4)) & 15; 100 101 const uint32_t cpufreq = (40000000 / divisor) * multiplier; 102 103 u_ar531x_cpu_freq = cpufreq; 104 u_ar531x_ahb_freq = cpufreq / 4; 105 u_ar531x_ddr_freq = 0; 106} 107 108/* 109 * This does not lock the CPU whilst doing the work! 110 */ 111static void 112ar5312_chip_device_reset(void) 113{ 114 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL, 115 AR5312_RESET_SYSTEM); 116} 117 118static void 119ar5312_chip_device_start(void) 120{ 121 uint32_t cfg0, cfg1; 122 uint32_t bank0, bank1; 123 uint32_t size0, size1; 124 125 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0); 126 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1); 127 128 bank0 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK0); 129 bank1 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK1); 130 131 size0 = bank0 ? (1 << (bank0 + 1)) : 0; 132 size1 = bank1 ? (1 << (bank1 + 1)) : 0; 133 134 size0 <<= 20; 135 size1 <<= 20; 136 137 printf("SDRMCTL %x %x %x %x\n", cfg0, cfg1, size0, size1); 138 139 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR); 140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE); 141// ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_WDOG_CTL, 0); 142 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0); 143 144 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE, 145 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) | 146 AR5312_ENABLE_ENET0 | AR5312_ENABLE_ENET1); 147 148} 149 150static int 151ar5312_chip_device_stopped(uint32_t mask) 152{ 153 uint32_t reg; 154 155 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL); 156 return ((reg & mask) == mask); 157} 158 159static void 160ar5312_chip_set_mii_speed(uint32_t unit, uint32_t speed) 161{ 162} 163 164/* Speed is either 10, 100 or 1000 */ 165static void 166ar5312_chip_set_pll_ge(int unit, int speed) 167{ 168} 169 170static void 171ar5312_chip_ddr_flush_ge(int unit) 172{ 173} 174 175static void 176ar5312_chip_soc_init(void) 177{ 178 179 u_ar531x_uart_addr = MIPS_PHYS_TO_KSEG1(AR5312_UART0_BASE); 180 181 u_ar531x_gpio_di = AR5312_GPIO_DI; 182 u_ar531x_gpio_do = AR5312_GPIO_DO; 183 u_ar531x_gpio_cr = AR5312_GPIO_CR; 184 u_ar531x_gpio_pins = AR5312_GPIO_PINS; 185 186 u_ar531x_wdog_ctl = AR5312_SYSREG_WDOG_CTL; 187 u_ar531x_wdog_timer = AR5312_SYSREG_WDOG_TIMER; 188 189} 190 191static uint32_t 192ar5312_chip_get_eth_pll(unsigned int mac, int speed) 193{ 194 return 0; 195} 196 197struct ar5315_cpu_def ar5312_chip_def = { 198 &ar5312_chip_detect_mem_size, 199 &ar5312_chip_detect_sys_frequency, 200 &ar5312_chip_device_reset, 201 &ar5312_chip_device_start, 202 &ar5312_chip_device_stopped, 203 &ar5312_chip_set_pll_ge, 204 &ar5312_chip_set_mii_speed, 205 &ar5312_chip_ddr_flush_ge, 206 &ar5312_chip_get_eth_pll, 207 &ar5312_chip_soc_init, 208}; 209