Lines Matching refs:ATH_READ_REG
99 bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
105 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
109 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
117 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
132 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
136 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
144 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
159 clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
197 reg = ATH_READ_REG(AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
212 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
221 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
230 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
330 reg = ATH_READ_REG(AR934X_GMAC_REG_ETH_CFG);
347 reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
449 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
455 ATH_READ_REG(AR71XX_GPIO_BASE + reg);