/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 22 namespace ARM_AM { namespace in namespace:llvm 25 default: return ARM_AM::no_shift; 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 33 //case ARMISD::RRX: return ARM_AM::rrx; 36 } // end namespace ARM_AM
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H A D | ARMLoadStoreOptimizer.cpp | 235 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) 236 : ARM_AM::getAM5Offset(OffField) * 4; 237 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField) 238 : ARM_AM::getAM5Op(OffField); 240 if (Op == ARM_AM::sub) 254 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) { 261 case ARM_AM::ia: return ARM::LDMIA; 262 case ARM_AM::da: return ARM::LDMDA; 263 case ARM_AM [all...] |
H A D | ARMBaseInstrInfo.cpp | 184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 185 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 187 if (ARM_AM::getSOImmVal(Amt) == -1) 198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 199 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 219 unsigned Amt = ARM_AM [all...] |
H A D | ARMISelDAGToDAG.cpp | 83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt); 168 return ARM_AM::getSOImmVal(Imm) != -1; 172 return ARM_AM::getSOImmVal(~Imm) != -1; 176 return ARM_AM::getT2SOImmVal(Imm) != -1; 180 return ARM_AM::getT2SOImmVal(~Imm) != -1; 521 ARM_AM::ShiftOpc ShOpcVal, 528 return ShOpcVal == ARM_AM::lsl && 589 ARM_AM::getSORegOpc(ARM_AM::lsl, PowerOfTwo), Loc, MVT::i32); 594 ARM_AM [all...] |
H A D | Thumb2InstrInfo.cpp | 251 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 321 int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal); 341 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 343 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 519 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 546 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 551 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && 597 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 598 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM [all...] |
H A D | ARMFastISel.cpp | 185 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 430 Imm = ARM_AM::getFP64Imm(Val); 433 Imm = ARM_AM::getFP32Imm(Val); 480 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 481 (ARM_AM::getSOImmVal(Imm) != -1); 1369 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1370 (ARM_AM::getSOImmVal(Imm) != -1); 1626 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1627 (ARM_AM::getSOImmVal(Imm) != -1); 2635 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM [all...] |
H A D | ARMBaseRegisterInfo.cpp | 522 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 523 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 530 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 531 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 536 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 537 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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H A D | ARMMCInstLower.cpp | 159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
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H A D | ARMInstructionSelector.cpp | 822 int FPImmEncoding = ARM_AM::getFP32Imm(FPImmValue); 834 int FPImmEncoding = ARM_AM::getFP64Imm(FPImmValue); 1062 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); 1064 return selectShift(ARM_AM::ShiftOpc::asr, MIB); 1066 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
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H A D | ARMTargetTransformInfo.cpp | 97 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 98 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 104 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 105 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 112 if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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H A D | ARMFrameLowering.cpp | 299 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)) 304 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)) 1151 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
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H A D | ARMExpandPseudoInsts.cpp | 884 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 885 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 2195 .addImm(ARM_AM::getSORegOpc( 2196 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 2208 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
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H A D | ARMISelLowering.cpp | 4501 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) && 4502 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) { 5760 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80); 5783 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff), 6764 unsigned EncodedVal = ARM_AM::createVMOVModImm(OpCmode, Imm); 6808 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal); 7380 if (ARM_AM [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 61 if (ShOpc != ARM_AM::rrx) { 105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM [all...] |
H A D | ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff 26 namespace ARM_AM { namespace in namespace:llvm 47 case ARM_AM::asr: return "asr"; 48 case ARM_AM::lsl: return "lsl"; 49 case ARM_AM::lsr: return "lsr"; 50 case ARM_AM::ror: return "ror"; 51 case ARM_AM::rrx: return "rrx"; 52 case ARM_AM::uxtw: return "uxtw"; 59 case ARM_AM::asr: return 2; 60 case ARM_AM [all...] |
H A D | ARMMCCodeEmitter.cpp | 234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 237 case ARM_AM::da: return 0; 238 case ARM_AM::ia: return 1; 239 case ARM_AM::db: return 2; 240 case ARM_AM::ib: return 3; 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 248 case ARM_AM::no_shift: 249 case ARM_AM::lsl: return 0; 250 case ARM_AM [all...] |
H A D | ARMAsmBackend.cpp | 518 if (ARM_AM::getSOImmVal(Value) == -1) { 523 return ARM_AM::getSOImmVal(Value) | (opc << 21); 793 Value = ARM_AM::getSOImmVal(Value); 800 Value = ARM_AM::getT2SOImmVal(Value);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 460 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 862 ARM_AM::ShiftOpc ShiftTy; 872 ARM_AM::ShiftOpc ShiftTy; 879 ARM_AM::ShiftOpc ShiftTy; 1120 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1292 return (ARM_AM::getSOImmVal(Value) != -1 || 1293 ARM_AM::getSOImmVal(-Value) != -1); 1310 return ARM_AM::getT2SOImmVal(Value) != -1; 1318 return ARM_AM [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1481 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1484 Shift = ARM_AM::lsl; 1487 Shift = ARM_AM::lsr; 1490 Shift = ARM_AM::asr; 1493 Shift = ARM_AM::ror; 1497 if (Shift == ARM_AM::ror && imm == 0) 1498 Shift = ARM_AM::rrx; 1520 ARM_AM::ShiftOpc Shift = ARM_AM [all...] |