Lines Matching refs:ARM_AM
460 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
862 ARM_AM::ShiftOpc ShiftTy;
872 ARM_AM::ShiftOpc ShiftTy;
879 ARM_AM::ShiftOpc ShiftTy;
1120 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1292 return (ARM_AM::getSOImmVal(Value) != -1 ||
1293 ARM_AM::getSOImmVal(-Value) != -1);
1310 return ARM_AM::getT2SOImmVal(Value) != -1;
1318 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1319 ARM_AM::getT2SOImmVal(~Value) != -1;
1328 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1329 ARM_AM::getT2SOImmVal(-Value) != -1;
1411 return ARM_AM::getSOImmVal(~Value) != -1;
1419 return ARM_AM::getSOImmVal(Value) == -1 &&
1420 ARM_AM::getSOImmVal(-Value) != -1;
1446 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1606 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1666 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1673 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1690 if (Memory.ShiftType == ARM_AM::no_shift)
1692 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1701 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1838 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1842 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2188 return ARM_AM::isNEONi16splat(Value);
2198 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2210 return ARM_AM::isNEONi32splat(Value);
2220 return ARM_AM::isNEONi32splat(~Value);
2486 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2497 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2557 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2564 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2613 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2877 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2881 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2885 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2898 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2902 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2921 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2925 Val = ARM_AM::getAM3Opc(AddSub, Val);
2929 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2940 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2949 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2953 Val = ARM_AM::getAM3Opc(AddSub, Val);
2971 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2975 Val = ARM_AM::getAM5Opc(AddSub, Val);
2993 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2997 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
3108 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3190 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3191 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3302 Value = ARM_AM::encodeNEONi16splat(Value);
3311 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3320 Value = ARM_AM::encodeNEONi32splat(Value);
3329 Value = ARM_AM::encodeNEONi32splat(~Value);
3526 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3540 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3691 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3709 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3841 if (Memory.ShiftType != ARM_AM::no_shift) {
3842 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3852 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3853 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3875 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3880 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4029 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
4030 .Case("asl", ARM_AM::lsl)
4031 .Case("lsl", ARM_AM::lsl)
4032 .Case("lsr", ARM_AM::lsr)
4033 .Case("asr", ARM_AM::asr)
4034 .Case("ror", ARM_AM::ror)
4035 .Case("rrx", ARM_AM::rrx)
4036 .Default(ARM_AM::no_shift);
4038 if (ShiftTy == ARM_AM::no_shift)
4055 if (ShiftTy == ARM_AM::rrx) {
4082 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4083 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4090 ShiftTy = ARM_AM::lsl;
4106 if (ShiftReg && ShiftTy != ARM_AM::rrx)
5359 int Enc = ARM_AM::getSOImmVal(Imm1);
5533 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5615 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5739 ARM_AM::no_shift, 0, 0, false,
5796 ARM_AM::no_shift, 0, Align,
5849 ARM_AM::no_shift, 0, 0,
5878 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5910 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5920 St = ARM_AM::lsl;
5922 St = ARM_AM::lsr;
5924 St = ARM_AM::asr;
5926 St = ARM_AM::ror;
5928 St = ARM_AM::rrx;
5930 St = ARM_AM::uxtw;
5937 if (St != ARM_AM::rrx) {
5957 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5958 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5962 St = ARM_AM::lsl;
6041 float RealVal = ARM_AM::getFPImmFloat(Val);
8607 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8680 if (ARM_AM::getSOImmVal(Value) != -1) {
8681 Value = ARM_AM::getSOImmVal(Value);
8684 else if (ARM_AM::getSOImmVal(~Value) != -1) {
8685 Value = ARM_AM::getSOImmVal(~Value);
8699 ARM_AM::getT2SOImmVal(Value) != -1)
8702 ARM_AM::getT2SOImmVal(~Value) != -1) {
9849 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
9851 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
9852 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
9853 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
9854 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
9884 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
9885 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
9888 if (Shift == ARM_AM::lsl && Amount == 0) {
9901 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
9902 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
9903 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
9904 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
9905 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
9930 ARM_AM::ShiftOpc ShiftTy;
9933 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
9934 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
9935 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
9936 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
9938 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
9955 ARM_AM::ShiftOpc ShiftTy;
9958 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
9959 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
9960 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
9961 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
9967 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
9969 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
9983 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
10069 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
10353 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10355 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10357 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10378 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10379 if (SOpc == ARM_AM::rrx) return false;
10391 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10392 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {