Lines Matching refs:ARM_AM
185 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
430 Imm = ARM_AM::getFP64Imm(Val);
433 Imm = ARM_AM::getFP32Imm(Val);
480 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
481 (ARM_AM::getSOImmVal(Imm) != -1);
1369 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1370 (ARM_AM::getSOImmVal(Imm) != -1);
1626 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1627 (ARM_AM::getSOImmVal(Imm) != -1);
2635 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2636 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2637 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2638 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2639 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2640 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2643 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2644 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2645 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2646 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2647 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2648 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2653 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2654 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2655 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2656 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2657 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2658 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2661 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2662 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2663 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2664 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2665 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2666 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2690 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2691 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2702 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2717 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2718 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2763 ARM_AM::ShiftOpc ShiftTy) {
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2809 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2877 return SelectShift(I, ARM_AM::lsl);
2879 return SelectShift(I, ARM_AM::lsr);
2881 return SelectShift(I, ARM_AM::asr);