/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZPostRewrite.cpp | 111 Register Src1Reg = MBBI->getOperand(1).getReg(); local 114 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg); 120 if (DestReg != Src1Reg && DestReg != Src2Reg) { 126 Src1Reg = DestReg; 139 if (DestReg != Src1Reg && DestReg == Src2Reg) { 141 std::swap(Src1Reg, Src2Reg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local 97 Src1Reg = MI.getOperand(1).getReg(); 100 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 142 Src1Reg = MI.getOperand(1).getReg(); 144 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 156 Src1Reg = MI.getOperand(0).getReg(); 157 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
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H A D | HexagonMCDuplexInfo.cpp | 191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local 324 Src1Reg = MCI.getOperand(0).getReg(); 326 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && 328 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { 332 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 340 Src1Reg = MCI.getOperand(0).getReg(); 342 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 359 Src1Reg = MCI.getOperand(0).getReg(); 361 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 369 Src1Reg [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 1177 Register Src1Reg = MI.getOperand(1).getReg(); local 1179 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); 1180 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); 1201 Register Src1Reg = MI.getOperand(1).getReg(); local 1204 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); 1205 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); 3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local 3309 Src1Reg = MI.getOperand(1).getReg(); 3313 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) 3346 Src1Reg 3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 275 Register Src1Reg = MI->getOperand(2).getReg(); local 291 .addReg(Src1Reg, getKillRegState(Src1Kill))
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 271 unsigned Src1Reg = 0) const;
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H A D | R600InstrInfo.cpp | 1242 unsigned Src1Reg) const { 1246 if (Src1Reg) { 1260 if (Src1Reg) { 1261 MIB.addReg(Src1Reg) // $src1
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H A D | AMDGPUInstructionSelector.cpp | 415 Register Src1Reg = I.getOperand(3).getReg(); local 436 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI)) 590 Register Src1Reg = I.getOperand(2).getReg(); local 591 LLT Src1Ty = MRI->getType(Src1Reg); 611 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); 625 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) 631 .addReg(Src1Reg) 653 Register Src1Reg = I.getOperand(3).getReg(); local 657 for (Register Reg : { DstReg, Src0Reg, Src1Reg })
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H A D | AMDGPURegisterBankInfo.cpp | 2995 Register Src1Reg = MI.getOperand(3).getReg(); local 2997 unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits(); 3002 OpdsMapping[3] = AMDGPU::getValueMapping(getRegBankID(Src1Reg, MRI, *TRI),
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H A D | SIInstrInfo.cpp | 2408 Register Src1Reg = Src1->getReg(); local 2410 Src0->setReg(Src1Reg);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1047 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); local 1051 if (!Src1Reg || !Src2Reg || !CondReg) 1069 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); 1942 unsigned Src1Reg = getRegForValue(I->getOperand(1)); local 1943 if (!Src0Reg || !Src1Reg) 1946 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); 1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2689 unsigned Src1Reg = getRegForValue(Src1Val); local 2690 if (!Src1Reg) 2700 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); 2703 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, 2819 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); local 2825 if (!Src1Reg || !Src2Reg) 2829 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, 2833 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, 4666 unsigned Src1Reg local 4744 unsigned Src1Reg = getRegForValue(I->getOperand(1)); local [all...] |
H A D | AArch64InstructionSelector.cpp | 1102 Register Src1Reg = I.getOperand(1).getReg(); local 1125 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); 1140 Register Src1Reg = I.getOperand(1).getReg(); local 1173 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg}); 2822 Register Src1Reg = I.getOperand(1).getReg(); local 2826 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB); 3777 Register Src1Reg = I.getOperand(1).getReg(); local 3778 const LLT Src1Ty = MRI.getType(Src1Reg); 3821 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder); 3850 {&AArch64::QQRegClass}, {Src1Reg}) [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 4200 Register Src1Reg = MI.getOperand(2).getReg(); local 4217 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 4236 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
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