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  • only in /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching refs:Src1Reg

1177       Register Src1Reg = MI.getOperand(1).getReg();
1179 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1180 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1201 Register Src1Reg = MI.getOperand(1).getReg();
1204 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1205 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3309 Src1Reg = MI.getOperand(1).getReg();
3313 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3346 Src1Reg = MI.getOperand(1).getReg();
3350 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3361 Src1Reg = MI.getOperand(0).getReg();
3362 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3363 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3855 Src1Reg = MI.getOperand(0).getReg();
3857 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3859 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3863 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3870 Src1Reg = MI.getOperand(0).getReg();
3872 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3887 Src1Reg = MI.getOperand(0).getReg();
3889 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3896 Src1Reg = MI.getOperand(0).getReg();
3899 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3900 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3906 Src1Reg = MI.getOperand(0).getReg();
3907 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3914 Src1Reg = MI.getOperand(0).getReg();
3915 if (isIntRegForSubInst(Src1Reg) &&
3967 Src1Reg = MI.getOperand(1).getReg();
3969 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&