Lines Matching refs:Src1Reg
1102 Register Src1Reg = I.getOperand(1).getReg();
1125 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg});
1140 Register Src1Reg = I.getOperand(1).getReg();
1173 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
2822 Register Src1Reg = I.getOperand(1).getReg();
2826 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
3777 Register Src1Reg = I.getOperand(1).getReg();
3778 const LLT Src1Ty = MRI.getType(Src1Reg);
3821 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder);
3850 {&AArch64::QQRegClass}, {Src1Reg})