Searched refs:Mips (Results 1 - 25 of 61) sorted by relevance

123

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips
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H A DMipsAsmBackend.cpp1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
48 case Mips::fixup_Mips_LO16:
49 case Mips::fixup_Mips_GPREL16:
50 case Mips::fixup_Mips_GPOFF_HI:
51 case Mips::fixup_Mips_GPOFF_LO:
52 case Mips::fixup_Mips_GOT_PAGE:
53 case Mips::fixup_Mips_GOT_OFST:
54 case Mips::fixup_Mips_GOT_DISP:
55 case Mips::fixup_Mips_GOT_LO16:
56 case Mips
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H A DMipsInstPrinter.cpp1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
9 // This class prints an Mips MCInst to a .s file.
36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
84 case Mips::RDHWR:
85 case Mips::RDHWR64:
89 case Mips::Save16:
94 case Mips::SaveX16:
99 case Mips::Restore16:
104 case Mips
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H A DMipsNaClELFStreamer.cpp1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
9 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
19 #include "Mips.h"
37 const unsigned IndirectBranchMaskReg = Mips::T6;
38 const unsigned LoadStoreStackMaskReg = Mips::T7;
59 if (MI.getOpcode() == Mips::JALR) {
63 return MI.getOperand(0).getReg() == Mips::ZERO;
65 return MI.getOpcode() == Mips::JR;
70 && MI.getOperand(0).getReg() == Mips::SP);
82 case Mips
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H A DMipsABIFlagsSection.cpp1 //===- MipsABIFlagsSection.cpp - Mips ELF ABI Flags Section ---------------===//
20 return Mips::Val_GNU_MIPS_ABI_FP_ANY;
22 return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
24 return Mips::Val_GNU_MIPS_ABI_FP_XX;
26 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
29 return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
30 : Mips::Val_GNU_MIPS_ABI_FP_64A;
31 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
52 return (uint8_t)Mips::AFL_REG_32;
H A DMipsMCCodeEmitter.cpp1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
76 case Mips::DSLL:
77 Inst.setOpcode(Mips::DSLL32);
79 case Mips::DSRL:
80 Inst.setOpcode(Mips::DSRL32);
82 case Mips::DSRA:
83 Inst.setOpcode(Mips::DSRA32);
85 case Mips::DROTR:
86 Inst.setOpcode(Mips::DROTR32);
101 if (Inst.getOpcode() == Mips
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H A DMipsABIFlagsSection.h1 //===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
67 Value |= (uint32_t)Mips
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H A DMipsELFObjectWriter.cpp1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
231 case Mips::fixup_Mips_16:
234 case Mips::fixup_Mips_32:
245 case Mips::fixup_Mips_Branch_PCRel:
246 case Mips::fixup_Mips_PC16:
248 case Mips::fixup_MICROMIPS_PC7_S1:
250 case Mips::fixup_MICROMIPS_PC10_S1:
252 case Mips::fixup_MICROMIPS_PC16_S1:
254 case Mips::fixup_MICROMIPS_PC26_S1:
256 case Mips
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
71 if ((Opc == Mips
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H A DMipsInstrInfo.cpp1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
9 // This file contains the Mips implementation of the TargetInstrInfo class.
40 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
61 BuildMI(MBB, MI, DL, get(Mips::NOP));
136 "# of Mips branch conditions must be <= 3!");
185 "Invalid Mips branch condition!");
281 case Mips::B:
282 case Mips::BAL:
283 case Mips
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H A DMipsRegisterInfo.cpp15 #include "Mips.h"
42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 return &Mips::GPRMM16RegClass;
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips
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H A DMipsExpandPseudo.cpp21 #include "Mips.h"
49 return "Mips pseudo instruction expansion pass";
84 unsigned ZERO = Mips::ZERO;
85 unsigned BNE = Mips::BNE;
86 unsigned BEQ = Mips::BEQ;
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH;
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips
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H A DMips16InstrInfo.cpp43 : MipsInstrInfo(STI, Mips::Bimm16) {}
75 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76 Mips::GPR32RegClass.contains(SrcReg))
77 Opc = Mips::MoveR3216;
78 else if (Mips::GPR32RegClass.contains(DestReg) &&
79 Mips::CPU16RegsRegClass.contains(SrcReg))
80 Opc = Mips::Move32R16;
81 else if ((SrcReg == Mips::HI0) &&
82 (Mips::CPU16RegsRegClass.contains(DestReg)))
83 Opc = Mips
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H A DMipsSERegisterInfo.cpp15 #include "Mips.h"
56 return &Mips::GPR32RegClass;
59 return &Mips::GPR64RegClass;
68 case Mips::LD_B:
69 case Mips::ST_B:
71 case Mips::LD_H:
72 case Mips::ST_H:
74 case Mips::LD_W:
75 case Mips::ST_W:
77 case Mips
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H A DMipsRegisterBankInfo.cpp9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
26 namespace Mips { namespace in namespace:llvm
71 } // end namespace Mips
82 using namespace Mips;
85 case Mips::GPR32RegClassID:
86 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
87 case Mips::GPRMM16MovePPairFirstRegClassID:
88 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
89 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
90 case Mips
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H A DMipsOptionRecord.h10 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
11 // specific ELF sections like .Mips.options. Specific records should subclass
14 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(TRI->getRegClass(Mips
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H A DMicroMipsSizeReduction.cpp13 #include "Mips.h"
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips
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H A DMipsInstructionSelector.cpp10 /// Mips.
91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
122 return &Mips::GPR32RegClass;
130 return &Mips::FGR32RegClass;
131 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
144 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
150 MachineInstr *Inst = B.buildInstr(Mips
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H A DMipsMachineFunction.cpp1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
36 return Mips::CPU16RegsRegClass;
39 return Mips::GPRMM16RegClass;
42 return Mips::GPR64RegClass;
44 return Mips::GPR32RegClass;
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
81 MF.getRegInfo().addLiveIn(Mips::T9_64);
82 MBB.addLiveIn(Mips::T9_64);
88 BuildMI(MBB, I, DL, TII.get(Mips
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H A DMipsBranchExpansion.cpp78 #include "Mips.h"
143 return "Mips Branch Expansion Pass";
371 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR;
372 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC;
373 unsigned JR_HB = ABI.IsN64() ? Mips::JR_HB64 : Mips::JR_HB;
374 unsigned JR_HB_R6 = ABI.IsN64() ? Mips::JR_HB64_R6 : Mips
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H A DMipsAsmPrinter.cpp1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
20 #include "Mips.h"
123 TmpInst0.setOpcode(Mips::JALR64);
128 TmpInst0.setOpcode(Mips::JRC16_MMR6);
130 TmpInst0.setOpcode(Mips::JALR);
135 TmpInst0.setOpcode(Mips::JR_MM);
138 TmpInst0.setOpcode(Mips::JR);
144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
204 if (InConstantPool && Opc != Mips
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H A DMips16ISelLowering.cpp30 "pseudos for Mips 16"),
125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
169 case Mips::SelBeqZ:
170 return emitSel16(Mips::BeqzRxImm16, MI, BB);
171 case Mips::SelBneZ:
172 return emitSel16(Mips::BnezRxImm16, MI, BB);
173 case Mips::SelTBteqZCmpi:
174 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
175 case Mips
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H A DMipsSEFrameLowering.cpp50 if (Mips::ACC64RegClass.contains(Src))
51 return std::make_pair((unsigned)Mips::PseudoMFHI,
52 (unsigned)Mips::PseudoMFLO);
54 if (Mips::ACC64DSPRegClass.contains(Src))
55 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
57 if (Mips::ACC128RegClass.contains(Src))
58 return std::make_pair((unsigned)Mips::PseudoMFHI64,
59 (unsigned)Mips::PseudoMFLO64);
117 case Mips
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
9 // This file is part of the Mips Disassembler.
14 #include "Mips.h"
47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
55 return STI.getFeatureBits()[Mips::FeatureMips32r6];
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
60 bool isGP64() const { return STI.getFeatureBits()[Mips
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