Lines Matching refs:Mips
29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
93 Opc = Mips::MOVE16_MM;
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
96 } else if (Mips::CCRRegClass.contains(SrcReg))
97 Opc = Mips::CFC1;
98 else if (Mips::FGR32RegClass.contains(SrcReg))
99 Opc = Mips::MFC1;
100 else if (Mips::HI32RegClass.contains(SrcReg)) {
101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
103 } else if (Mips::LO32RegClass.contains(SrcReg)) {
104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFHI_DSP;
108 else if (Mips::LO32DSPRegClass.contains(SrcReg))
109 Opc = Mips::MFLO_DSP;
110 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
115 else if (Mips::MSACtrlRegClass.contains(SrcReg))
116 Opc = Mips::CFCMSA;
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119 if (Mips::CCRRegClass.contains(DestReg))
120 Opc = Mips::CTC1;
121 else if (Mips::FGR32RegClass.contains(DestReg))
122 Opc = Mips::MTC1;
123 else if (Mips::HI32RegClass.contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LO32RegClass.contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HI32DSPRegClass.contains(DestReg))
128 Opc = Mips::MTHI_DSP;
129 else if (Mips::LO32DSPRegClass.contains(DestReg))
130 Opc = Mips::MTLO_DSP;
131 else if (Mips::DSPCCRegClass.contains(DestReg)) {
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_S;
145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
146 Opc = Mips::FMOV_D32;
147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
148 Opc = Mips::FMOV_D64;
149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150 if (Mips::GPR64RegClass.contains(SrcReg))
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152 else if (Mips::HI64RegClass.contains(SrcReg))
153 Opc = Mips::MFHI64, SrcReg = 0;
154 else if (Mips::LO64RegClass.contains(SrcReg))
155 Opc = Mips::MFLO64, SrcReg = 0;
156 else if (Mips::FGR64RegClass.contains(SrcReg))
157 Opc = Mips::DMFC1;
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160 if (Mips::HI64RegClass.contains(DestReg))
161 Opc = Mips::MTHI64, DestReg = 0;
162 else if (Mips::LO64RegClass.contains(DestReg))
163 Opc = Mips::MTLO64, DestReg = 0;
164 else if (Mips::FGR64RegClass.contains(DestReg))
165 Opc = Mips::DMTC1;
167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168 if (Mips::MSA128BRegClass.contains(SrcReg))
169 Opc = Mips::MOVE_V;
190 case Mips::OR_MM:
191 case Mips::OR:
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
195 case Mips::OR64:
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
209 case Mips::WRDSP:
210 case Mips::WRDSP_MM:
213 case Mips::RDDSP:
214 case Mips::RDDSP_MM:
254 if (Mips::GPR32RegClass.hasSubClassEq(RC))
255 Opc = Mips::SW;
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
257 Opc = Mips::SD;
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
259 Opc = Mips::STORE_ACC64;
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
261 Opc = Mips::STORE_ACC64DSP;
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
263 Opc = Mips::STORE_ACC128;
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
265 Opc = Mips::STORE_CCOND_DSP;
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
267 Opc = Mips::SWC1;
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
269 Opc = Mips::SDC1;
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
271 Opc = Mips::SDC164;
273 Opc = Mips::ST_B;
276 Opc = Mips::ST_H;
279 Opc = Mips::ST_W;
282 Opc = Mips::ST_D;
283 else if (Mips::LO32RegClass.hasSubClassEq(RC))
284 Opc = Mips::SW;
285 else if (Mips::LO64RegClass.hasSubClassEq(RC))
286 Opc = Mips::SD;
287 else if (Mips::HI32RegClass.hasSubClassEq(RC))
288 Opc = Mips::SW;
289 else if (Mips::HI64RegClass.hasSubClassEq(RC))
290 Opc = Mips::SD;
291 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
292 Opc = Mips::SWDSP;
298 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
300 SrcReg = Mips::K0;
301 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
302 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
303 SrcReg = Mips::K0_64;
304 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
305 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
306 SrcReg = Mips::K0;
307 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
308 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
309 SrcReg = Mips::K0_64;
329 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
330 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
332 if (Mips::GPR32RegClass.hasSubClassEq(RC))
333 Opc = Mips::LW;
334 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
335 Opc = Mips::LD;
336 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
337 Opc = Mips::LOAD_ACC64;
338 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
339 Opc = Mips::LOAD_ACC64DSP;
340 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
341 Opc = Mips::LOAD_ACC128;
342 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
343 Opc = Mips::LOAD_CCOND_DSP;
344 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
345 Opc = Mips::LWC1;
346 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
347 Opc = Mips::LDC1;
348 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
349 Opc = Mips::LDC164;
351 Opc = Mips::LD_B;
354 Opc = Mips::LD_H;
357 Opc = Mips::LD_W;
360 Opc = Mips::LD_D;
361 else if (Mips::HI32RegClass.hasSubClassEq(RC))
362 Opc = Mips::LW;
363 else if (Mips::HI64RegClass.hasSubClassEq(RC))
364 Opc = Mips::LD;
365 else if (Mips::LO32RegClass.hasSubClassEq(RC))
366 Opc = Mips::LW;
367 else if (Mips::LO64RegClass.hasSubClassEq(RC))
368 Opc = Mips::LD;
369 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
370 Opc = Mips::LWDSP;
382 unsigned Reg = Mips::K0;
383 unsigned LdOp = Mips::MTLO;
384 if (DestReg == Mips::HI0)
385 LdOp = Mips::MTHI;
388 Reg = Mips::K0_64;
389 if (DestReg == Mips::HI0_64)
390 LdOp = Mips::MTHI64;
392 LdOp = Mips::MTLO64;
411 case Mips::RetRA:
414 case Mips::ERet:
417 case Mips::PseudoMFHI:
418 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
420 case Mips::PseudoMFHI_MM:
421 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
423 case Mips::PseudoMFLO:
424 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
426 case Mips::PseudoMFLO_MM:
427 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
429 case Mips::PseudoMFHI64:
430 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
432 case Mips::PseudoMFLO64:
433 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
435 case Mips::PseudoMTLOHI:
436 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
438 case Mips::PseudoMTLOHI64:
439 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
441 case Mips::PseudoMTLOHI_DSP:
442 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
444 case Mips::PseudoMTLOHI_MM:
445 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
447 case Mips::PseudoCVT_S_W:
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
450 case Mips::PseudoCVT_D32_W:
451 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
454 case Mips::PseudoCVT_S_L:
455 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
457 case Mips::PseudoCVT_D64_W:
458 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
461 case Mips::PseudoCVT_D64_L:
462 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
464 case Mips::BuildPairF64:
467 case Mips::BuildPairF64_64:
470 case Mips::ExtractElementF64:
473 case Mips::ExtractElementF64_64:
476 case Mips::MIPSeh_return32:
477 case Mips::MIPSeh_return64:
491 case Mips::BEQ: return Mips::BNE;
492 case Mips::BEQ_MM: return Mips::BNE_MM;
493 case Mips::BNE: return Mips::BEQ;
494 case Mips::BNE_MM: return Mips::BEQ_MM;
495 case Mips::BGTZ: return Mips::BLEZ;
496 case Mips::BGEZ: return Mips::BLTZ;
497 case Mips::BLTZ: return Mips::BGEZ;
498 case Mips::BLEZ: return Mips::BGTZ;
499 case Mips::BGTZ_MM: return Mips::BLEZ_MM;
500 case Mips::BGEZ_MM: return Mips::BLTZ_MM;
501 case Mips::BLTZ_MM: return Mips::BGEZ_MM;
502 case Mips::BLEZ_MM: return Mips::BGTZ_MM;
503 case Mips::BEQ64: return Mips::BNE64;
504 case Mips::BNE64: return Mips::BEQ64;
505 case Mips::BGTZ64: return Mips::BLEZ64;
506 case Mips::BGEZ64: return Mips::BLTZ64;
507 case Mips::BLTZ64: return Mips::BGEZ64;
508 case Mips::BLEZ64: return Mips::BGTZ64;
509 case Mips::BC1T: return Mips::BC1F;
510 case Mips::BC1F: return Mips::BC1T;
511 case Mips::BC1T_MM: return Mips::BC1F_MM;
512 case Mips::BC1F_MM: return Mips::BC1T_MM;
513 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
514 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
515 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
516 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
517 case Mips::BEQZC: return Mips::BNEZC;
518 case Mips::BNEZC: return Mips::BEQZC;
519 case Mips::BLEZC: return Mips::BGTZC;
520 case Mips::BGEZC: return Mips::BLTZC;
521 case Mips::BGEC: return Mips::BLTC;
522 case Mips::BGTZC: return Mips::BLEZC;
523 case Mips::BLTZC: return Mips::BGEZC;
524 case Mips::BLTC: return Mips::BGEC;
525 case Mips::BGEUC: return Mips::BLTUC;
526 case Mips::BLTUC: return Mips::BGEUC;
527 case Mips::BEQC: return Mips::BNEC;
528 case Mips::BNEC: return Mips::BEQC;
529 case Mips::BC1EQZ: return Mips::BC1NEZ;
530 case Mips::BC1NEZ: return Mips::BC1EQZ;
531 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
532 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
533 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
534 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
535 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
536 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
537 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
538 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
539 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
540 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
541 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
542 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
543 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
544 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
545 case Mips::BEQZC64: return Mips::BNEZC64;
546 case Mips::BNEZC64: return Mips::BEQZC64;
547 case Mips::BEQC64: return Mips::BNEC64;
548 case Mips::BNEC64: return Mips::BEQC64;
549 case Mips::BGEC64: return Mips::BLTC64;
550 case Mips::BGEUC64: return Mips::BLTUC64;
551 case Mips::BLTC64: return Mips::BGEC64;
552 case Mips::BLTUC64: return Mips::BGEUC64;
553 case Mips::BGTZC64: return Mips::BLEZC64;
554 case Mips::BGEZC64: return Mips::BLTZC64;
555 case Mips::BLTZC64: return Mips::BGEZC64;
556 case Mips::BLEZC64: return Mips::BGTZC64;
557 case Mips::BBIT0: return Mips::BBIT1;
558 case Mips::BBIT1: return Mips::BBIT0;
559 case Mips::BBIT032: return Mips::BBIT132;
560 case Mips::BBIT132: return Mips::BBIT032;
561 case Mips::BZ_B: return Mips::BNZ_B;
562 case Mips::BZ_H: return Mips::BNZ_H;
563 case Mips::BZ_W: return Mips::BNZ_W;
564 case Mips::BZ_D: return Mips::BNZ_D;
565 case Mips::BZ_V: return Mips::BNZ_V;
566 case Mips::BNZ_B: return Mips::BZ_B;
567 case Mips::BNZ_H: return Mips::BZ_H;
568 case Mips::BNZ_W: return Mips::BZ_W;
569 case Mips::BNZ_D: return Mips::BZ_D;
570 case Mips::BNZ_V: return Mips::BZ_V;
611 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
612 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
614 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
646 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
647 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
648 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
649 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
650 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
651 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
652 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
653 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
654 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
655 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
656 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
657 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
658 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
659 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
660 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
661 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
662 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
663 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
664 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
665 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
666 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
667 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
668 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
669 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
677 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
678 .addReg(Mips::RA_64, RegState::Undef);
680 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
681 .addReg(Mips::RA, RegState::Undef);
692 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
733 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
734 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
758 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
761 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
777 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
788 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
802 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
803 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
807 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
815 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
842 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
858 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
859 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
866 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
877 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
878 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
879 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
880 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;