Lines Matching refs:Mips
50 if (Mips::ACC64RegClass.contains(Src))
51 return std::make_pair((unsigned)Mips::PseudoMFHI,
52 (unsigned)Mips::PseudoMFLO);
54 if (Mips::ACC64DSPRegClass.contains(Src))
55 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
57 if (Mips::ACC128RegClass.contains(Src))
58 return std::make_pair((unsigned)Mips::PseudoMFHI64,
59 (unsigned)Mips::PseudoMFLO64);
117 case Mips::LOAD_CCOND_DSP:
120 case Mips::STORE_CCOND_DSP:
123 case Mips::LOAD_ACC64:
124 case Mips::LOAD_ACC64DSP:
127 case Mips::LOAD_ACC128:
130 case Mips::STORE_ACC64:
131 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
133 case Mips::STORE_ACC64DSP:
134 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
136 case Mips::STORE_ACC128:
137 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
139 case Mips::BuildPairF64:
143 case Mips::BuildPairF64_64:
147 case Mips::ExtractElementF64:
151 case Mips::ExtractElementF64_64:
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
306 && I->getOperand(3).getReg() == Mips::SP) {
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
371 && I->getOperand(3).getReg() == Mips::SP) {
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
419 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
462 if (Mips::AFGR64RegClass.contains(Reg)) {
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
466 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
480 } else if (Mips::FGR64RegClass.contains(Reg)) {
551 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
568 // hazards. Pre R2 Mips relies on an implementation defined number
591 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
597 MBB.addLiveIn(Mips::COP013);
598 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
599 .addReg(Mips::COP013)
603 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
604 .addReg(Mips::K0)
611 MBB.addLiveIn(Mips::COP014);
612 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
613 .addReg(Mips::COP014)
617 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
622 MBB.addLiveIn(Mips::COP012);
623 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
624 .addReg(Mips::COP012)
628 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
636 unsigned SrcReg = Mips::ZERO;
641 SrcReg = Mips::K0;
657 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
661 .addReg(Mips::K1)
665 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
666 .addReg(Mips::ZERO)
669 .addReg(Mips::K1)
674 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
675 .addReg(Mips::ZERO)
678 .addReg(Mips::K1)
682 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
683 .addReg(Mips::K1)
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
754 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
761 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
765 .addReg(Mips::K1)
769 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
773 .addReg(Mips::K1)
807 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
814 bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
815 Reg == Mips::HI0 || Reg == Mips::HI0_64);
822 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
823 Reg = Mips::K0;
825 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
826 Reg = Mips::K0_64;
828 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
868 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
870 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
896 Mips::GPR64RegClass : Mips::GPR32RegClass;
913 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;