Lines Matching refs:Mips
1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
36 return Mips::CPU16RegsRegClass;
39 return Mips::GPRMM16RegClass;
42 return Mips::GPR64RegClass;
44 return Mips::GPR32RegClass;
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
81 MF.getRegInfo().addLiveIn(Mips::T9_64);
82 MBB.addLiveIn(Mips::T9_64);
88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91 .addReg(Mips::T9_64);
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
109 MF.getRegInfo().addLiveIn(Mips::T9);
110 MBB.addLiveIn(Mips::T9);
117 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
141 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
144 MF.getRegInfo().addLiveIn(Mips::V0);
145 MBB.addLiveIn(Mips::V0);
146 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
147 .addReg(Mips::V0).addReg(Mips::T9);
155 ? Mips::GPR64RegClass
156 : Mips::GPR32RegClass;
168 const TargetRegisterClass &RC = Mips::GPR32RegClass;