/freebsd-11.0-release/sys/dev/drm2/ |
H A D | drm_dp_helper.c | 45 int lane) 47 int i = DP_LANE0_1_STATUS + (lane >> 1); 48 int s = (lane & 1) * 4; 58 int lane; local 64 for (lane = 0; lane < lane_count; lane++) { 65 lane_status = dp_get_lane_status(link_status, lane); 76 int lane; local 79 for (lane 44 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument 88 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument 101 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument [all...] |
H A D | drm_dp_helper.h | 333 int lane); 335 int lane);
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/freebsd-11.0-release/sys/contrib/alpine-hal/eth/ |
H A D | al_hal_eth_kr.h | 154 * @param lane lane number 160 enum al_eth_an_lt_lane lane, 167 * @param lane lane number 173 enum al_eth_an_lt_lane lane, 180 * @param lane lane number 186 enum al_eth_an_lt_lane lane, 193 * @param lane lan [all...] |
H A D | al_hal_eth_kr.c | 212 enum al_eth_an_lt_lane lane) 218 al_assert(lane == AL_ETH_AN__LT_LANE_0); 233 switch (lane) { 275 al_err("%s: Unknown Lane %d\n", __func__, lane); 281 al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__, 282 (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val); 291 enum al_eth_an_lt_lane lane, 310 switch (lane) { 356 al_err("%s: Unknown Lane %d\n", __func__, lane); 362 al_dbg("[%s]: %s - (%s) lane 208 al_eth_an_lt_reg_read( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_regs_ids reg_id, enum al_eth_an_lt_regs an_lt, enum al_eth_an_lt_lane lane) argument 287 al_eth_an_lt_reg_write( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_regs_ids reg_id, enum al_eth_an_lt_regs an_lt, enum al_eth_an_lt_lane lane, uint16_t val) argument 497 al_eth_lp_coeff_up_get( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, struct al_eth_kr_coef_up_data *lpcoeff) argument 527 al_eth_lp_status_report_get( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, struct al_eth_kr_status_report_data *status) argument 554 al_eth_ld_coeff_up_set( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, struct al_eth_kr_coef_up_data *ldcoeff) argument 585 al_eth_ld_status_report_set( struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, struct al_eth_kr_status_report_data *status) argument 614 al_eth_kr_receiver_frame_lock_get(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 625 al_eth_kr_startup_proto_prog_get(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 636 al_eth_kr_training_status_fail_get(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 646 al_eth_receiver_ready_set(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 897 al_eth_kr_an_start(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, al_bool next_page_enable, al_bool lt_enable) argument 960 al_eth_kr_lt_restart(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 970 al_eth_kr_lt_stop(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 979 al_eth_kr_lt_initialize(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane) argument 999 al_eth_kr_lt_frame_lock_wait(struct al_hal_eth_adapter *adapter, enum al_eth_an_lt_lane lane, uint32_t timeout) argument [all...] |
/freebsd-11.0-release/sys/contrib/alpine-hal/ |
H A D | al_hal_serdes.h | 137 * Parallel loopback from the PMA receive lane data ports, to the 138 * transmit lane data ports 318 * SERDES lane Rx rate change software flow enable 324 * @param lane 325 * The SERDES lane within the group 330 enum al_serdes_lane lane); 333 * SERDES lane Rx rate change software flow disable 339 * @param lane 340 * The SERDES lane within the group 345 enum al_serdes_lane lane); [all...] |
H A D | al_hal_serdes.c | 77 enum al_serdes_lane lane, 85 enum al_serdes_lane lane, 92 * SERDES core reg/lane read 107 * SERDES core reg/lane write 118 enum al_serdes_lane lane, 124 * SERDES core masked reg/lane write 139 enum al_serdes_lane lane); 152 enum al_serdes_lane lane); 163 enum al_serdes_lane lane, 242 enum al_serdes_lane lane, 239 al_serdes_lane_read( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_reg_type type, uint16_t offset, uint8_t *data) argument 290 al_serdes_lane_write( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_reg_type type, uint16_t offset, uint8_t data) argument 597 al_serdes_lane_rx_rate_change_sw_flow_en( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 612 al_serdes_lane_rx_rate_change_sw_flow_dis( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 622 al_serdes_lane_pcie_rate_override_enable_set( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, al_bool en) argument 641 al_serdes_lane_pcie_rate_override_is_enabled( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 658 al_serdes_lane_pcie_rate_get( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 676 al_serdes_lane_pcie_rate_set( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_pcie_rate rate) argument 695 al_serdes_lane_pm_set( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_pm rx_pm, enum al_serdes_pm tx_pm) argument 812 al_serdes_pma_hard_reset_lane( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, al_bool enable) argument 860 al_serdes_loopback_control( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_lb_mode mode) argument 959 al_serdes_bist_tx_enable( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, al_bool enable) argument 1003 al_serdes_bist_rx_enable( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, al_bool enable) argument 1027 al_serdes_bist_rx_status( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, al_bool *is_locked, al_bool *err_cnt_overflow, uint16_t *err_cnt) argument 1111 al_serdes_grp_lane_write( struct al_serdes_group_info *grp_info, enum al_serdes_lane lane, enum al_serdes_reg_type type, uint16_t offset, uint8_t data) argument 1157 al_serdes_grp_lane_masked_write( struct al_serdes_group_info *grp_info, enum al_serdes_lane lane, enum al_serdes_reg_type type, uint16_t offset, uint8_t mask, uint8_t data) argument 1171 _al_serdes_lane_rx_rate_change_sw_flow_dis( struct al_serdes_group_info *grp_info, enum al_serdes_lane lane) argument 1207 int lane; local 1215 _al_serdes_lane_rx_rate_change_sw_flow_en_cond( struct al_serdes_group_info *grp_info, enum al_serdes_lane lane) argument 1296 int lane; local 1304 al_serdes_eye_measure_run( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, uint32_t timeout, unsigned int *value) argument 1343 al_serdes_eye_diag_sample( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, unsigned int x, int y, unsigned int timeout, unsigned int *value) argument 1472 al_serdes_tx_deemph_set( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, uint32_t c_zero, uint32_t c_plus_1, uint32_t c_minus_1) argument 1506 al_serdes_tx_deemph_get( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, uint32_t *c_zero, uint32_t *c_plus_1, uint32_t *c_minus_1) argument 1544 al_serdes_tx_deemph_inc( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_tx_deemph_param param) argument 1602 al_serdes_tx_deemph_dec( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, enum al_serdes_tx_deemph_param param) argument 1653 al_serdes_tx_deemph_preset( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 1674 al_serdes_signal_is_detected( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 1690 al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, struct al_serdes_adv_tx_params *params) argument 1767 al_serdes_tx_advanced_params_get(struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, struct al_serdes_adv_tx_params *tx_params) argument 1806 al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, struct al_serdes_adv_rx_params *params) argument 2579 al_serdes_rx_advanced_params_get(struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, struct al_serdes_adv_rx_params* rx_params) argument 2652 al_serdes_rx_equalization( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane) argument 2849 al_serdes_calc_eye_size( struct al_serdes_obj *obj, enum al_serdes_group grp, enum al_serdes_lane lane, int* width, int* height) argument [all...] |
H A D | al_hal_pcie.c | 592 al_dbg("PCIe %d: Set EQ (0x%08x) for lane %d, %d\n", pcie_port->port_id, eq_control, i, i + 1); 1048 pcie_port->regs->axi.status.lane[0] = ®s->axi.status.lane0; 1049 pcie_port->regs->axi.status.lane[1] = ®s->axi.status.lane1; 1050 pcie_port->regs->axi.status.lane[2] = ®s->axi.status.lane2; 1051 pcie_port->regs->axi.status.lane[3] = ®s->axi.status.lane3; 1108 pcie_port->regs->axi.status.lane[0] = ®s->axi.status.lane0; 1109 pcie_port->regs->axi.status.lane[1] = ®s->axi.status.lane1; 1110 pcie_port->regs->axi.status.lane[2] = ®s->axi.status.lane2; 1111 pcie_port->regs->axi.status.lane[3] = ®s->axi.status.lane3; 1171 pcie_port->regs->axi.status.lane[ 1973 al_pcie_lane_status_get( struct al_pcie_port *pcie_port, unsigned int lane, struct al_pcie_lane_status *status) argument [all...] |
H A D | al_hal_serdes_regs.h | 137 struct serdes_lane lane[4]; /* [0x200] */ member in struct:al_serdes_regs
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H A D | al_hal_pcie.h | 341 /** PCIe gen 3 standard per lane equalization parameters */ 488 /** PCIe lane status */ 739 * @brief get lane status 743 * @param lane 744 * PCIe lane 746 * Pointer to returned structure for lane status 751 unsigned int lane,
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H A D | al_hal_pcie_regs.h | 286 uint32_t *lane[AL_MAX_NUM_OF_LANES]; member in struct:al_pcie_axi_status
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/freebsd-11.0-release/sys/contrib/octeon-sdk/ |
H A D | cvmx-qlm.h | 107 * @param lane Lane in QLM to get 112 extern uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name); 118 * @param lane Lane in QLM to set, or -1 for all lanes 122 extern void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value);
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H A D | cvmx-helper-errata.c | 304 int lane; local 313 for (lane=0; lane<4; lane++) 315 /* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
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H A D | cvmx-qlm.c | 77 * new data => lane 3 => lane 2 => lane 1 => lane 0 => data out 82 * new data => lane 0 => lane 1 => lane 2 => lane 3 => data out 322 * @param lane Lane in QLM to get 327 uint64_t cvmx_qlm_jtag_get(int qlm, int lane, cons argument 353 cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value) argument [all...] |
H A D | cvmx-sriomaintx-defs.h | 2505 * This register is used to monitor PHY status on each lane. They are documented here to assist in 2506 * debugging only. The lane numbers take into account the lane swap pin. 2946 * This register contains status information about the local lane transceiver. 2955 the lane is assigned. */ 2956 uint32_t lane : 4; /**< Lane Number within the port. */ member in struct:cvmx_sriomaintx_lane_x_status_0::cvmx_sriomaintx_lane_x_status_0_s 2973 controlled by the lane receiver and at least 2975 1 = The lane receiver controls no adaptive 3006 uint32_t lane : 4; 3559 000 = Single-lane, Lan [all...] |
/freebsd-11.0-release/sys/arm/nvidia/tegra124/ |
H A D | tegra124_xusbpadctl.c | 152 xusbpadctl_mux_function(const struct padctl_lane *lane, char *fnc_name) argument 156 for (i = 0; i < lane->nmux; i++) { 157 if (strcmp(fnc_name, lane->mux[i]) == 0) 166 const struct padctl_lane *lane, struct lane_cfg *cfg) 172 reg = bus_read_4(sc->mem_res, lane->reg); 174 tmp = xusbpadctl_mux_function(lane, cfg->function); 177 "Unknown function %s for lane %s\n", cfg->function, 181 reg &= ~(lane->mask << lane->shift); 182 reg |= (tmp & lane 165 xusbpadctl_config_lane(struct xusbpadctl_softc *sc, char *lane_name, const struct padctl_lane *lane, struct lane_cfg *cfg) argument 217 const struct padctl_lane *lane; local [all...] |
/freebsd-11.0-release/sys/dev/drm2/radeon/ |
H A D | atombios_dp.c | 304 int lane; local 306 for (lane = 0; lane < lane_count; lane++) { 307 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 308 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 310 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 311 lane, 331 for (lane = 0; lane < [all...] |
/freebsd-11.0-release/contrib/ofed/management/opensm/opensm/ |
H A D | osm_ucast_lash.c | 95 unsigned lane; member in struct:_switch::routing_table 205 int dest_switch, int lane) 218 v = cdg_vertex_matrix[lane][sw][i_next_switch]; 223 cdg_vertex_matrix[lane][sw][i_next_switch] = NULL; 237 cdg_vertex_matrix[lane][i_next_switch] 357 int lane) 370 if (cdg_vertex_matrix[lane][sw][next_switch] == NULL) { 389 cdg_vertex_matrix[lane][sw][next_switch] = v; 391 v = cdg_vertex_matrix[lane][sw][next_switch]; 430 int dest_switch, int lane) 204 remove_semipermanent_depend_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 356 generate_cdg_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 429 set_temp_depend_to_permanent_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument 459 remove_temp_depend_for_sp(lash_t * p_lash, int sw, int dest_switch, int lane) argument [all...] |
/freebsd-11.0-release/sys/dev/bxe/ |
H A D | bxe_elink.c | 2610 /* Use lane 1 (of lanes 0-3) */ 2619 /* Use lane 1 (of lanes 0-3) */ 4046 uint8_t lane = 0; local 4077 lane = (port<<1) + path; 4092 lane = path << 1 ; 4094 return lane; 4113 /* In Dual-lane mode, two lanes are joined together, 4369 uint8_t lane = elink_get_warpcore_lane(phy, params); local 4376 lane; 4435 * i.e. reset the lane (i 4551 uint16_t lane = elink_get_warpcore_lane(phy, params); local 4564 uint16_t lane, i, cl72_ctrl, an_adv = 0, val; local 4718 uint16_t val16, i, lane; local 4786 uint16_t misc1_val, tap_val, tx_driver_val, lane, val; local 4969 elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc, struct elink_phy *phy, uint16_t lane) argument 5125 elink_warpcore_clear_regs(struct elink_phy *phy, struct elink_params *params, uint16_t lane) argument 5221 uint16_t gp2_status_reg0, lane; local 5246 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5288 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5330 uint16_t lane = elink_get_warpcore_lane(phy, params); local 5435 uint16_t val16, lane; local 5491 uint32_t lane; local 6530 uint8_t lane; local 7321 uint8_t lane = elink_get_warpcore_lane(int_phy, params); local 9492 uint8_t lane = elink_get_warpcore_lane(phy, params); local 14829 uint16_t base_page, next_page, not_kr2_device, lane; local [all...] |
/freebsd-11.0-release/usr.sbin/tcpdump/tcpdump/ |
H A D | Makefile | 81 print-lane.c \
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/freebsd-11.0-release/sys/dev/drm2/i915/ |
H A D | intel_dp.c | 164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 702 DRM_DEBUG_KMS("DP link computation with max lane count %i " 720 DRM_DEBUG_KMS("DP link bw %02x lane " 783 * Find the lane count in the intel_encoder private 1521 int lane; local 1525 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1526 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 1527 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); [all...] |
H A D | intel_display.c | 4389 * In Valleyview PLL and program lane counter registers are exposed 4438 /* Now program lane control registers */ 5348 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", 5365 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5382 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5423 int target_clock, pixel_multiplier, lane, link_bw; local 5442 lane = 0; 5446 intel_edp_link_config(edp_encoder, &lane, &link_bw); 5452 * Hence the bw of each lane in terms of the mode signal 5466 if (!lane) [all...] |
/freebsd-11.0-release/sys/dev/mlx5/mlx5_core/ |
H A D | mlx5_port.c | 514 int lane = 0; local 526 lane = MLX5_GET(pmlp_reg, out, lane0_module_mapping); 527 *module_num = lane & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
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/freebsd-11.0-release/contrib/tcpdump/ |
H A D | Makefile.in | 147 print-lane.c \
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/freebsd-11.0-release/contrib/libpcap/ |
H A D | scanner.l | 284 lane return LANE;
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/freebsd-11.0-release/contrib/binutils/gas/config/ |
H A D | tc-arm.c | 1766 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1784 int lane = -1; 1843 if (lane == -1) 1844 lane = NEON_INTERLEAVE_LANES; 1845 else if (lane != NEON_INTERLEAVE_LANES) 1882 if (lane == -1) 1883 lane = atype.index; 1884 else if (lane != atype.index) 1890 else if (lane == -1) 1891 lane 1782 int lane = -1; local [all...] |